connectal

Connectal is a framework for software-driven hardware development.

Stars

2

Forks

0

Language

Bluespec

Last Updated

May 24, 2022

Similar Repos
Repo Language Stars Description Updated At
Shell 2 A framework for test driven Linux software development. Oct 30, 2023
    BlueAXI
Bluespec 4 None Mar 07, 2023
    BlueLib
Bluespec 4 None Dec 06, 2022
Bluespec 2 an implementation of a MIPS processor in BlueSpec System Verilog Nov 30, 2021
Bluespec 28 MAERI public release Apr 14, 2022
Bluespec 42 MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/) Jun 26, 2022
Bluespec 92 A collection of common Bluespec interfaces/modules. Jul 27, 2022
Bluespec 11 (WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog Feb 26, 2022
Bluespec 25 A place to share libraries and utilities that don't belong in the core bsc repo Apr 10, 2023
Bluespec 3 Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence. Feb 26, 2023
Bluespec 42 The BERI and CHERI processor and hardware platform Oct 28, 2022
Bluespec 5 Bluespec ISA Description framework Dec 24, 2021
Bluespec 4 Bit-string pattern matching for BSV Dec 09, 2020
    BlueBasics
Bluespec 5 None Dec 14, 2022
Bluespec 34 A generic test bench written in Bluespec Apr 05, 2023
Bluespec 12 A Bluespec SystemVerilog library of miscellaneous components Apr 04, 2023
Bluespec 4 A library of specific implementations of cheri and providing an abstract interface to those implementations Jan 27, 2023
Bluespec 2 A CHERI enabled simulation SOC using PISM and a TagController module Apr 03, 2020
Bluespec 7 RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance Apr 11, 2023
Bluespec 2 A BSV libary providing features similar to the Stmt sub-language May 18, 2022
Bluespec 14 RISC-V BSV Specification Dec 12, 2021
    RVFI-DII-utils
Bluespec 2 None Apr 06, 2023
Bluespec 4 Multi-level tag controller for emulating a tagged memory using an in-memory table. Feb 21, 2022
Bluespec 13 RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT Apr 21, 2023
Bluespec 2 Unify and centralise the interface to the Piccolo / Flute / Toooba cores Jan 30, 2022
Bluespec 3 Greenland ice borehole temperature profiles Apr 16, 2023
    dogbunnypuzzle-quint
Bluespec 2 None Apr 14, 2023
Bluespec 316 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。 May 16, 2023
Bluespec 3 Recognize Gymnotus electric organ discharges in real-time within microseconds Jan 20, 2022
Bluespec 2 Bluespec SystemVerilog implementation of the Keccak primitive (SHA-3) May 09, 2023
Bluespec 2 Turn several Zybo Z7-20 GPIO ports into UARTs Aug 15, 2022
Bluespec 5 CONNECT: CONfigurable NEtwork Creation Tool Feb 09, 2023
Bluespec 6 MIT6.175 & MIT6.375 Study Notes Jul 04, 2023
Bluespec 16 q3k's hardware monorepo Mar 26, 2022
    MIT_6.175
Bluespec 2 None Jun 14, 2023
Bluespec 4 CometBFT team public knowledge base. Always a work-in-progress. Jun 11, 2023
Bluespec 4 A high-throughput, parameterized, parallel crc hardware implementation. May 27, 2023
Bluespec 7 RoCEv2 hardware implementation in Bluespec SystemVerilog Oct 28, 2023
Bluespec 2 Hardware components to protect enclave pages from being accessed by untrusted cores Jul 26, 2023
    OpenSMART
Bluespec 2 None Jul 25, 2023
    learn_mit_bluespec
Bluespec 6 None Jan 26, 2024
    cumulus-library
Bluespec 2 None May 14, 2024
Ruby 5 Behaviour Driven Development framework for Ruby Aug 13, 2019
Ruby 2 Behaviour Driven Development framework for Ruby Aug 13, 2019
Ruby 2 Behaviour Driven Development framework for Ruby Aug 13, 2019
Ruby 2 Behaviour Driven Development framework for Ruby Aug 13, 2019
Ruby 3 Behaviour Driven Development framework for Ruby Aug 13, 2019
Ruby 2 Behaviour Driven Development framework for Ruby Aug 13, 2019
Ruby 8 Behaviour Driven Development framework for Ruby Aug 13, 2019
Ruby 3 Behaviour Driven Development framework for Ruby Aug 13, 2019