|
Verilog |
18 |
HDL code for the MATRIX Voice's Spartan 6 FPGA http://voice.matrix.one |
Nov 21, 2022 |
|
None |
2 |
Spartan-7 FPGA development board. |
May 03, 2023 |
|
Eagle |
3 |
The prototyping board for Xilinx Spartan-II FPGA processor. |
Jan 21, 2022 |
|
VHDL |
8 |
FPGA-based synthesizer in VHDL for the Xilinx Spartan-3A and Spartan-3E Starter Kits |
May 02, 2023 |
|
Python |
4 |
Amaranth HDL examples for the Ulx4m FPGA board |
Jul 18, 2022 |
|
None |
3 |
HDL things for FPGA and ASIC |
Nov 03, 2021 |
|
Verilog |
9 |
OV7670 (Verilog HDL)Drive for FPGA |
Apr 06, 2023 |
|
Verilog |
2 |
SoC FPGA interface HDL codes |
Jun 04, 2022 |
|
VHDL |
2 |
Hardware implementation of IDEA algorithm on the Spartan-3E FPGA. |
Mar 20, 2022 |
|
C |
2 |
Xilinx Spartan-3E FPGA; taximeter, stopwatch, etc.; verilog |
Dec 30, 2020 |
|
None |
2 |
references to introductions/tutorials for HDL, FPGA, hardware design |
Apr 19, 2023 |
|
C |
75 |
(RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC products |
Apr 04, 2022 |
|
Verilog |
3 |
Spartan-7 FPGA implementation of Ben Eater's 6502 breadboard computer |
May 26, 2022 |
|
Python |
9 |
An FPGA core for glitching circuits, written with Amaranth HDL. |
Aug 11, 2022 |
|
Tcl |
48 |
FPGA reference design for the the Swerv EH1 Core |
Mar 17, 2022 |
|
Tcl |
33 |
Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards |
Apr 22, 2023 |
|
Python |
9 |
FPGA implementation of an ADAT receiver/transmitter using amaranth HDL |
Jan 09, 2022 |
|
None |
7 |
This repository lists some awesome public HDL and FPGA projects. |
May 11, 2023 |
|
SystemVerilog |
3 |
Cozim - FPGA based Computer Architecture Simulator written in SystemVerilog HDL. |
Apr 12, 2021 |
|
MATLAB |
11 |
This repository contains FPGA/HDL demonstrations several beamforming and radar designs. Simulink models and MATLAB reference … |
Aug 10, 2022 |
|
VHDL |
2 |
Hardware based on a Xilinx Spartan 6 FPGA for capturing HDMI and DVI data. |
May 05, 2022 |
|
Python |
2 |
Synapse: Matrix reference homeserver |
Mar 08, 2023 |
|
Python |
2 |
Synapse: Matrix reference homeserver |
Apr 14, 2022 |
|
None |
2 |
Synapse: Matrix reference homeserver |
Oct 09, 2022 |
|
Python |
2 |
Synapse: Matrix reference homeserver |
Feb 07, 2023 |
|
C++ |
22 |
An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM). |
Aug 19, 2022 |
|
C++ |
2 |
An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM). |
Dec 01, 2022 |
|
Python |
109 |
Sygnal: reference Push Gateway for Matrix |
Aug 23, 2022 |
|
C++ |
52 |
Matrix Operation Library for FPGA https://xilinx.github.io/gemx/ |
Apr 11, 2022 |
|
Verilog |
2 |
Verilog HDL code for SM4 algorithm. |
Jul 07, 2022 |
|
HTML |
3 |
The website for Spartan Project's decentralized chat service. (including PHP code) |
May 24, 2023 |
|
Verilog |
4 |
Xilinx Spartan 3E & VHDL - Phase rangefiner / Abstract distance measurement with FFT on … |
May 01, 2023 |
|
Python |
2 |
deprecated FPGA code for the hexastorm |
Aug 05, 2020 |
|
Verilog |
27 |
An FPGA/PCI Device Reference Platform |
Aug 08, 2022 |
|
None |
10 |
Examples for the Spartan HPC cluster. |
Sep 02, 2019 |
|
Verilog |
6 |
Verilog HDL and HDL in general basics through code examples. |
Jun 17, 2022 |
|
Verilog |
4 |
This repository contains MATLAB code which can be used to generate simulink model and HDL … |
Mar 21, 2023 |
|
Python |
219 |
Sydent: Reference Matrix Identity Server |
Jul 20, 2022 |
|
Python |
142 |
Command line admin tool for Synapse (the Matrix reference homeserver) |
Apr 24, 2023 |
|
Verilog |
3 |
HDL & FPGA 学习和规范。CC-BY-NC-SA 4.0。 |
May 12, 2022 |
|
Verilog |
9 |
Line coding and clock recovery for a fibre optic link, running on a Spartan 6 … |
Jun 05, 2022 |
|
Verilog |
12 |
The source code for the XTRX FPGA image |
Aug 12, 2022 |
|
None |
3 |
Proposing and managing changes to The Creator's Galaxy |
Apr 30, 2022 |
|
C |
5 |
FPGA code for NeTV2 |
May 08, 2021 |
|
C |
5 |
FPGA code for NeTV2 |
Feb 05, 2023 |
|
Jupyter Notebook |
2 |
Tutorials for the Minispec HDL |
Jan 10, 2022 |
|
JavaScript |
7 |
DApp for Spartan Swap |
Jan 21, 2022 |
|
Verilog |
2 |
This project aims to implement a password cracker on FPGA with Verilog HDL. |
Feb 10, 2024 |
|
C |
36 |
Tools, runtime code, and HDL source for the moxie processor core. |
Apr 07, 2022 |
|
Python |
4 |
Generator for CRC HDL code (VHDL, Verilog, MyHDL) |
Jun 24, 2022 |