|
VHDL |
5 |
Hardware Description Language Translator |
May 25, 2022 |
|
C++ |
3 |
Minispec Hardware Description Language |
Apr 17, 2022 |
|
Go |
3 |
Hardware Description Language Server |
Jan 12, 2023 |
|
Scala |
34 |
A Hardware Pipeline Description Language |
Apr 06, 2023 |
|
Haskell |
7 |
Functional computer hardware description language |
Nov 05, 2022 |
|
JavaScript |
80 |
Hardware description language (HDL) parser, and Hardware simulator. |
Apr 18, 2023 |
|
Rust |
171 |
Veryl: A Modern Hardware Description Language |
Apr 22, 2023 |
|
C++ |
2 |
Description language to define hardware drivers |
Apr 24, 2023 |
|
Slice |
2 |
Experiments with the Silice Hardware Description Language |
Jul 18, 2022 |
|
F# |
3 |
Interactive Hardware Description Language/Block Diagram Editor |
Mar 06, 2022 |
|
C++ |
79 |
ACT hardware description language and core tools. |
Apr 26, 2023 |
|
Python |
6 |
Python implementation of a Hardware Description Language (HDL) |
Nov 17, 2021 |
|
Scala |
6 |
Security-typed version of the FIRRTL hardware description language |
Jun 09, 2022 |
|
C# |
3 |
A hardware description language, simulator, and 32 bit CPU |
Jun 30, 2020 |
|
None |
602 |
Hardware Description Languages |
Aug 02, 2022 |
|
Python |
19 |
Hardware Description Library |
Apr 19, 2023 |
|
None |
2 |
Hardware Description Languages |
Apr 28, 2022 |
|
None |
2 |
Hardware Description Languages |
Mar 21, 2023 |
|
JavaScript |
4 |
Parser for nand2tetris HDL (Hardware Description Language), written in JavaScript |
Jan 09, 2022 |
|
VHDL |
7 |
Singing Very High Speed Integrated Circuit Hardware Description Language Board |
Oct 16, 2020 |
|
Clojure |
3 |
An experimental, interactive, Lispy, object-oriented, hardware description language (HDL). |
Apr 08, 2023 |
|
Verilog |
7 |
Asynchronous AES core written using the Balsa hardware description language |
Oct 19, 2022 |
|
SystemVerilog |
3 |
A hardware description and hardware verification language used for Digital Circuit Design Course (EE1010) |
Jan 11, 2023 |
|
Tcl |
33 |
Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards |
Apr 22, 2023 |
|
Emacs Lisp |
13 |
Emacs major mode for editing NAND hardware description language files (.hdl) |
Sep 20, 2022 |
|
Python |
2 |
Sign Language Translator |
Mar 19, 2022 |
|
CSS |
4 |
B - Language Translator |
Jan 30, 2023 |
|
Python |
2 |
Tunic language translator |
May 11, 2023 |
|
Java |
2 |
Language Translator Application |
Nov 08, 2022 |
|
Python |
4 |
Python package for using Python as a hardware description and verification language |
Apr 20, 2022 |
|
C++ |
8 |
Compiler for a high-level hardware description language with automatic pipeline synthesis |
Nov 20, 2022 |
|
JavaScript |
2 |
Hardware description for software engineers. |
Sep 09, 2016 |
|
Verilog |
6 |
DMA Hardware Description with Verilog |
Feb 28, 2023 |
|
Python |
3 |
Language translator using Python Programming language |
Nov 10, 2021 |
|
Python |
6 |
Mathematica Language Parser/Translator |
Sep 04, 2021 |
|
Java |
2 |
Language translator desktop application |
Jan 28, 2023 |
|
Rust |
2 |
A hardware description language using Rust syntax, combined with an event-driven simulator. |
May 06, 2022 |
|
SystemVerilog |
4 |
Moving Average |
Jan 28, 2022 |
|
SystemVerilog |
4 |
Collaborative project to create an advanced GPU for the Microcom computer. |
Jun 12, 2022 |
|
SystemVerilog |
4 |
SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 … |
May 25, 2022 |
|
SystemVerilog |
4 |
This example .BMP generator and ASCII script file reader can be adapted to test code … |
May 25, 2022 |
|
SystemVerilog |
4 |
FPGA low latency 10GBASE-R PCS |
May 19, 2022 |
|
SystemVerilog |
4 |
A continually growing system verilog parts library |
Dec 09, 2021 |
|
SystemVerilog |
4 |
基于FPGA的CNN图像分类系统 |
May 06, 2022 |
|
SystemVerilog |
4 |
Intel CPU Garage Challenge |
Jun 13, 2022 |
|
SystemVerilog |
4 |
system verilog course labs |
Nov 09, 2021 |
|
SystemVerilog |
4 |
Hardware-Software codesign project. |
Dec 12, 2021 |
|
SystemVerilog |
4 |
Verilog code for a simple synth module; developed on TinyFPGA BX |
Jul 18, 2022 |
verilator-dynamic-scheduler-tests
|
SystemVerilog |
4 |
None |
Mar 04, 2022 |
|
SystemVerilog |
4 |
まともなRISC-V CPU |
Jul 18, 2022 |