|
Python |
59 |
Python Scripts for Conical GCode Slicing |
Apr 15, 2023 |
|
Kotlin |
4 |
Python style string slicing for Kotlin |
Dec 12, 2020 |
|
Python |
25 |
Unified slicing for all Python data structures. |
Aug 05, 2022 |
|
None |
8 |
Collection of List slicing patterns for Python |
May 25, 2023 |
|
Verilog |
8 |
Verilog Implementation of a 32-bit Multicycle CPU |
Oct 19, 2021 |
|
Verilog |
3 |
Verilog implementation of the 32-bit RISC processor. |
May 23, 2022 |
|
None |
2 |
web-based IDE for 8-bit programming and Verilog development |
Jan 28, 2023 |
|
G-code |
12 |
Default Slicing profiles for various slicing softwares |
Oct 31, 2022 |
|
JavaScript |
2 |
Python like list slicing in javascript. |
Apr 10, 2017 |
|
Verilog |
6 |
Verilog implementation of Ben Eater's 8-bit breadboard computer |
May 26, 2022 |
|
Verilog |
2 |
A 32-bit Timer/Counter/Capture Soft IP (Verilog) |
Aug 16, 2023 |
|
None |
4 |
6502-like CPU core with 16-bit data and 32-bit address in Verilog |
Mar 02, 2018 |
|
VHDL |
9 |
Python Frontend For VHDL And Verilog |
Dec 04, 2023 |
|
Python |
4 |
A python library for slicing nD images along splines. |
Feb 15, 2023 |
|
Verilog |
3 |
An Verilog implementation of a 16 bit processor, codenamed Artemis |
Sep 16, 2021 |
|
Verilog |
2 |
32-bit RISC Processor design using Harvard Architecture in Verilog. |
May 05, 2022 |
|
TeX |
9 |
Verilog implementation of 16-bit multi-cycle RISC15 processor design |
Feb 15, 2023 |
|
Rust |
2 |
(System)Verilog verification code injector - for automatically testing designs against single bit failures |
Dec 01, 2023 |
|
C |
2 |
A 32-bit MIPS processor developed in Verilog based on pipeline |
Mar 16, 2022 |
|
Python |
12 |
Simple Verilog Parser In Python |
Jun 02, 2022 |
|
C++ |
31 |
Lightweight tool for slicing |
May 09, 2023 |
|
Python |
6 |
Slicing LIST |
Jul 02, 2022 |
|
None |
11 |
UVM/systemverilog/verilog/python VIM IDE |
Aug 31, 2022 |
|
HTML |
3 |
A toolbox for program slicing |
Oct 04, 2022 |
|
Racket |
22 |
Slicing git repositories. |
Oct 17, 2021 |
|
JavaScript |
5 |
slicing react boostrap |
Aug 06, 2023 |
|
None |
2 |
32-bit Python wheels for wxPython |
Apr 29, 2023 |
|
CoffeeScript |
7 |
Atom linter for Verilog, using icarus verilog. |
May 10, 2021 |
|
Python |
4 |
Python-based Hardware Design Processing Toolkit for Verilog HDL |
Dec 07, 2021 |
|
SystemVerilog |
7 |
Verilog module for flexible instantiation of ROM/RAM of arbitrary depth and bit width. Automatically reduce … |
Mar 29, 2023 |
|
Python |
3 |
Example of OFDM in Python and Verilog |
Mar 28, 2023 |
|
Rust |
8 |
Slicing for utf8 strings in Rust. |
Apr 15, 2022 |
|
Python |
84 |
Slic3r plugin for slicing within OctoPrint |
Jul 26, 2022 |
|
G-code |
14 |
Slicing Guide for ZONESTAR 3D printer |
Oct 09, 2022 |
|
C# |
69 |
View-aligned mesh slicing for Unity. |
Nov 01, 2022 |
|
Rust |
22 |
Utilities for enhanced slicing and indexing |
Apr 27, 2023 |
|
Verilog |
2 |
16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course) |
Jun 07, 2021 |
|
Vue |
15 |
Project slicing design UI |
Apr 21, 2022 |
|
JavaScript |
116 |
Slicing and coding game |
Jul 15, 2022 |
|
Python |
32 |
Volume Slicing and Editing |
Jan 07, 2023 |
|
CSS |
3 |
starting template html slicing |
Feb 17, 2023 |
|
Python |
6 |
Dynamic time-slicing method |
Mar 28, 2023 |
|
Dart |
2 |
slicing ui design travel_app |
Feb 20, 2023 |
|
Julia |
49 |
Type stable array slicing |
May 10, 2023 |
|
TypeScript |
2 |
Slicing UI Design Getstatic |
May 27, 2023 |
|
None |
2 |
Portable Python 2.7 for Windows 64-bit |
May 08, 2022 |
|
Python |
12 |
Simple Python parser for extracting HDL (VHDL or Verilog) documentation |
Mar 31, 2023 |
|
Verilog |
17 |
This fork family includes the 6502 upgraded to 32-bit address bus, in Verilog HDL |
May 02, 2022 |
|
Python |
3 |
A Verilog Code Test Bench Generator using Python |
Mar 08, 2022 |
|
Python |
37 |
A data acquisition framework in Python and Verilog. |
Mar 10, 2023 |