|
TypeScript |
186 |
Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code |
Aug 11, 2022 |
|
Rust |
4 |
Format Verilog/SystemVerilog code |
Nov 09, 2022 |
|
TypeScript |
82 |
SystemVerilog support in VS Code |
Oct 07, 2022 |
|
None |
11 |
UVM/systemverilog/verilog/python VIM IDE |
Aug 31, 2022 |
|
Python |
23 |
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator |
Apr 13, 2023 |
|
SystemVerilog |
6 |
Wiznet w5300 driver code, powered by SystemVerilog |
Feb 12, 2024 |
|
Python |
4 |
Helper for running python code indirectly |
Aug 21, 2022 |
|
None |
2 |
Inject code into running Python processes |
Dec 21, 2021 |
|
Python |
14 |
Inject code into running Python processes |
May 22, 2023 |
|
Python |
5 |
Code editor for writing and running python code. |
Aug 22, 2022 |
|
C |
5 |
A fork of - python vpi interface for systemverilog. |
Jul 13, 2022 |
|
SystemVerilog |
5 |
Snake game implemented in SystemVerilog, running on the Digilent Nexys DDR 4. |
Jun 23, 2022 |
|
TypeScript |
13 |
SystemVerilog language server client for Visual Studio Code |
Jul 01, 2022 |
|
SystemVerilog |
8 |
SystemVerilog code for image processing tasks like demosaicing |
Jul 09, 2022 |
|
JavaScript |
4 |
SystemVerilog Linter |
Jul 02, 2022 |
|
Rust |
162 |
SystemVerilog linter |
Aug 09, 2022 |
|
Rust |
2 |
SystemVerilog linter |
Apr 27, 2023 |
|
Rust |
2 |
systemverilog format |
Nov 02, 2022 |
|
None |
5 |
SystemVerilog Toys |
Feb 12, 2022 |
|
Python |
2 |
Inject arbitrary code into running Python processes |
Jan 08, 2013 |
|
Python |
2 |
Projects running on Circuit Python code base |
Jul 12, 2022 |
|
Python |
2 |
Running Rust code from Python using PyO3 |
Apr 12, 2023 |
|
Python |
17 |
Utilities for running Python code in production |
Jan 13, 2022 |
|
Python |
2 |
Django app for running Python code interview |
Jan 14, 2022 |
|
Python |
21 |
A system to Instrument running Python code |
Mar 07, 2023 |
|
Python |
5 |
Python bindings for slang, a library for compiling SystemVerilog |
Aug 09, 2022 |
|
C++ |
125 |
This tool translates synthesizable SystemC code to synthesizable SystemVerilog. |
Jul 17, 2022 |
|
SystemVerilog |
2 |
Generate a gray code of arbitrary width in SystemVerilog |
Apr 12, 2022 |
|
SystemVerilog |
9 |
Verilog/SystemVerilog Guide |
Sep 07, 2022 |
|
SystemVerilog |
222 |
Common SystemVerilog components |
Aug 20, 2022 |
|
Rust |
230 |
SystemVerilog language server |
Aug 12, 2022 |
|
SystemVerilog |
3 |
SystemVerilog Coding Style |
May 29, 2021 |
|
None |
3 |
SystemVerilog Style Guidelines |
Dec 13, 2020 |
|
Java |
49 |
SystemVerilog Development Environment |
Apr 13, 2022 |
|
Rust |
5 |
A SystemVerilog elaborator |
Jan 01, 2022 |
|
None |
2 |
Common SystemVerilog components |
Jan 29, 2022 |
|
VimL |
3 |
SystemVerilog syntax highlighting |
Aug 28, 2019 |
|
Python |
5 |
An abstract language model of SystemVerilog (incl. Verilog) written in Python. |
May 04, 2022 |
|
Shell |
2 |
Exercism exercises in SystemVerilog. |
May 13, 2022 |
|
C++ |
23 |
Fiber-based SystemVerilog Simulator. |
Jun 05, 2022 |
|
C |
3 |
Simple microprocessor in SystemVerilog. |
Feb 22, 2023 |
|
SystemVerilog |
12 |
Reflection API for SystemVerilog |
Sep 12, 2022 |
|
Haskell |
365 |
SystemVerilog to Verilog conversion |
May 22, 2023 |
|
SystemVerilog |
3 |
SystemVerilog IP design & verification |
Sep 23, 2023 |
|
Python |
2 |
Example Python code for running the mango-explorer marketmaker |
Apr 11, 2022 |
|
Python |
2 |
An example of running a Fortran code from Python |
Oct 15, 2020 |
|
None |
2 |
All you need to write HDLs (Verilog-HDL/VHDL/SystemVerilog/Bluespec SystemVerilog) |
Jan 13, 2023 |
|
Python |
3 |
Pyverilog-sv2v is converting systemverilog code to verilog code. The converted script in verilog is used … |
May 25, 2023 |
|
Python |
22 |
Code for running Petroleum Experts OpenServer API commands in Python |
Jul 13, 2022 |
|
Python |
3 |
A Python library containing supporting code for running SRT tests |
Sep 08, 2022 |