|
Scala |
2 |
RTL blocks compatible with the Rocket Chip Generator |
Aug 25, 2022 |
|
Scala |
8 |
RTL blocks compatible with the Rocket Chip Generator |
Mar 31, 2023 |
|
Verilog |
17 |
Chisel Project for Integrating RTL code into SDAccel |
Jan 06, 2023 |
|
Scala |
25 |
sha256d mining chip written by chisel. |
Jun 16, 2022 |
|
Scala |
17 |
OpenSoC Fabric - A Network-On-Chip Generator |
Jan 03, 2021 |
|
Scala |
3 |
OpenSoC Fabric - A Network-On-Chip Generator |
Sep 20, 2023 |
|
Scala |
9 |
JTAG generator in Chisel |
Jun 15, 2022 |
|
Verilog |
34 |
FFT generator using Chisel |
May 07, 2023 |
|
SystemVerilog |
2 |
RTL code for the DPU chip designed for irregular graphs |
Feb 20, 2023 |
|
Scala |
6 |
Rocket Chip Generator |
Mar 14, 2021 |
|
Scala |
2311 |
Rocket Chip Generator |
Aug 11, 2022 |
|
Scala |
2 |
Rocket Chip Generator |
Dec 18, 2021 |
|
None |
8 |
Rocket Chip Generator |
Dec 18, 2022 |
|
None |
5 |
Rocket Chip Generator |
Jan 31, 2023 |
|
Scala |
2 |
Rocket Chip Generator |
Mar 25, 2024 |
|
Scala |
2 |
Rocket Chip Generator |
Apr 15, 2024 |
|
SystemVerilog |
11 |
Network on Chip for MPSoC |
Jul 07, 2022 |
|
Scala |
2 |
A Chisel Generator of Numerically Controlled Oscillators |
Oct 06, 2022 |
|
Jupyter Notebook |
691 |
Generator Bootcamp Material: Learn Chisel the Right Way |
Aug 23, 2022 |
|
Verilog |
502 |
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators |
May 20, 2023 |
|
Verilog |
36 |
A verilog implementation for Network-on-Chip |
May 06, 2023 |
|
Scala |
2 |
Tilelink Uncached Lightweight (TL-UL) On-Chip Communication Architecture Protocol implemented in Scala & CHISEL |
Apr 12, 2022 |
|
Scala |
37 |
For contributions of Chisel IP to the chisel community. |
Aug 13, 2022 |
|
Python |
14 |
Gate-level visualization generator for SKY130-based chip designs. |
May 26, 2023 |
|
C++ |
4 |
SystemC UVM environment generator for PyGears components. RTL simulated with Verilator |
May 06, 2022 |
|
Python |
15 |
Random number generator from rtl-sdr supported radio dongles |
May 06, 2022 |
|
Java |
3 |
Chisel compatibility for Ztones |
May 13, 2021 |
|
Java |
5 |
Metallurgy compatibility for Chisel |
Dec 30, 2018 |
|
Rust |
27 |
Kubernetes Operator for Chisel |
Jul 05, 2023 |
|
TeX |
16 |
Chisel Cheatsheet |
Aug 02, 2022 |
|
SystemVerilog |
6 |
chisel-rv32 |
Mar 24, 2023 |
|
Scala |
2 |
Example Chisel modules and Chisel -> Verilog Wake flow |
Nov 23, 2022 |
|
Scala |
5 |
An RTL generator for a last-level shared inclusive TileLink cache controller |
Apr 11, 2023 |
|
VHDL |
7 |
Pipework components is VHDL library for NoC(Network on Chip). |
Mar 24, 2022 |
|
VHDL |
2 |
Pipework components is VHDL library for NoC(Network on Chip). |
Jan 13, 2022 |
|
Scala |
2 |
CHISEL API for plug n play connection of Caches in CHISEL designs |
Apr 20, 2023 |
|
C++ |
36 |
Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused) |
Apr 28, 2023 |
|
C++ |
46 |
Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused) |
Apr 26, 2023 |
|
Go |
126 |
C# Wrapper around Chisel from https://github.com/jpillora/chisel |
Aug 01, 2022 |
|
Scala |
14 |
BFM Tester for Chisel HDL |
Aug 16, 2022 |
|
C |
17 |
Various examples for Chisel HDL |
Sep 21, 2022 |
|
Scala |
3 |
Some playground for Chisel experiments |
Nov 15, 2022 |
|
Scala |
6 |
Chisel Implementation Tutorial |
Feb 22, 2022 |
|
Java |
8 |
Unlimited Chisel Works |
Oct 19, 2022 |
|
Verilog |
4 |
µIR Chisel library |
Mar 29, 2022 |
|
None |
2 |
Chisel release tooling |
May 26, 2024 |
|
Python |
3 |
Emulator for CHIP-8, CHIP-48, Super-CHIP 1.0, Super-CHIP 1.1 and XO-CHIP Systems |
May 05, 2023 |
|
C |
8 |
Creates a network interface for a LoRa chip connected over serial |
May 19, 2020 |
|
VHDL |
13 |
A Statically-scheduled TDM Network-on-Chip for Real-Time Systems |
Jul 31, 2022 |
|
C++ |
10 |
Deep Neural Network inference using Xilinx Zynq-7000 chip. |
Jul 16, 2022 |