|
C++ |
13 |
RISC-V vector extension ISA simulation |
Apr 14, 2023 |
|
JavaScript |
2 |
RISC-V ISA helpers |
Aug 01, 2022 |
|
C |
8 |
RISC-V Functional ISA Simulator |
May 21, 2022 |
|
None |
80 |
ISA 8-bit Backplane |
May 17, 2023 |
|
VHDL |
374 |
A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz |
May 11, 2023 |
|
Scala |
515 |
educational microarchitectures for risc-v isa |
Aug 05, 2022 |
|
C |
1374 |
Spike, a RISC-V ISA Simulator |
Jun 26, 2022 |
|
None |
8 |
Spike, a RISC-V ISA Simulator |
Jan 31, 2023 |
|
Haskell |
48 |
Galois RISC-V ISA Formal Tools |
Mar 26, 2023 |
|
C |
2 |
Spike, a RISC-V ISA Simulator |
Dec 14, 2021 |
|
C |
3 |
Spike, a RISC-V ISA Simulator |
Sep 07, 2021 |
|
C |
2 |
Spike, a RISC-V ISA Simulator |
Dec 01, 2022 |
|
C |
3 |
Spike, a RISC-V ISA Simulator |
Apr 14, 2023 |
|
C |
4 |
Spike, a RISC-V ISA Simulator |
Feb 14, 2022 |
|
C |
2 |
Spike, a RISC-V ISA Simulator |
Nov 06, 2023 |
|
Assembly |
67 |
ISA 8-Bit Ethernet Controller |
May 17, 2023 |
|
Python |
4 |
An assembler for the RISC-V ISA |
May 15, 2016 |
|
Shell |
1005 |
RISC-V Tools (ISA Simulator and Tests) |
Aug 21, 2022 |
|
None |
2 |
CoreDSL descriptions of the RISC-V ISA |
Apr 26, 2022 |
|
Python |
26 |
Python Model of the RISC-V ISA |
Jun 27, 2022 |
|
SystemVerilog |
56 |
Vector processor for RISC-V vector ISA |
May 08, 2023 |
|
Verilog |
2 |
Pipelined CPU microarchitecture RISC-V ISA RV32I. |
Dec 09, 2023 |
|
C |
5 |
Adding support for risc-v 128-bit extension to QEMU |
Dec 01, 2022 |
|
CoffeeScript |
4 |
Easy bit manipulation |
Jan 28, 2023 |
|
Verilog |
2 |
32 bit RISC Processor |
Jun 11, 2021 |
|
Verilog |
17 |
32-bit RISC processor |
May 16, 2022 |
|
Shell |
6 |
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests) |
Mar 20, 2022 |
|
Rust |
12 |
A RISC-V ISA simulator written in Rust |
Aug 03, 2021 |
|
SystemVerilog |
4 |
A synthesizable RISC processor implementing the Power ISA |
Mar 16, 2022 |
|
Julia |
2 |
bit manipulation and static bit vectors |
Mar 28, 2024 |
|
None |
4 |
Z80 PC with 8 bit ISA backplane |
Jul 16, 2022 |
|
Julia |
7 |
Julia Bit Manipulation Functions |
Nov 29, 2021 |
|
Circom |
2 |
Bit manipulation in Circom |
Sep 17, 2023 |
|
SystemVerilog |
6 |
RISC processor 8bit (AVR ISA), RTL based on 'navre' |
Jul 20, 2017 |
|
Rust |
282 |
CKB's vm, based on open source RISC-V ISA |
Aug 05, 2022 |
|
SystemVerilog |
5 |
system verilog implementation of RISC-V ISA for FPGA |
Sep 20, 2022 |
|
C |
68 |
A port of FreeRTOS for the RISC-V ISA |
Jan 28, 2023 |
|
C |
2 |
a RISC-V ISA c compiler ported from chibicc |
Jul 12, 2023 |
|
Python |
2 |
Primitive CPU implementation in Python using RISC-V ISA |
Mar 02, 2024 |
|
C |
8 |
32-bit RISC-V microcontroller |
May 11, 2022 |
|
C |
16 |
32-bit RISC-V Emulator |
Mar 02, 2022 |
|
C |
2 |
RISC-V 64-bit kernel |
Oct 12, 2022 |
|
None |
10 |
Miniature 8-bit ISA CompactFlash Interface + Boot ROM |
May 02, 2023 |
|
None |
25 |
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA … |
Jul 28, 2022 |
|
Verilog |
2 |
This is the RISC-V ISA implementation by Group 2 |
Jun 27, 2022 |
|
None |
61 |
Port of the Yocto Project to the RISC-V ISA |
Jun 28, 2021 |
|
Haskell |
120 |
A formal semantics of the RISC-V ISA in Haskell |
Jul 21, 2022 |
|
Haskell |
3 |
Extensible implementation of the RISC-V ISA based on FreeMonads |
Jul 10, 2023 |
|
JavaScript |
2 |
Bare-bones bit manipulation language. |
Jul 06, 2017 |
|
Verilog |
5 |
Simple Pipelined 32 bit RISC Processor |
Jul 16, 2022 |