|
VHDL |
26 |
Implementation of CNN network based on VHDL |
Nov 17, 2023 |
|
VHDL |
21 |
AUTOMATIC VHDL GENERATION FOR CNN MODELS |
Apr 19, 2023 |
|
VHDL |
3 |
VHDL implementation |
Mar 29, 2022 |
|
VHDL |
9 |
VHDL Implementation |
Feb 24, 2023 |
|
VHDL |
16 |
CNN-to-FPGA-framework for small CNN, written in VHDL and Python |
Mar 21, 2023 |
|
VHDL |
25 |
VHDL Gameboy implementation |
Apr 09, 2023 |
|
VHDL |
9 |
MessagePack implementation for VHDL |
Aug 25, 2020 |
|
VHDL |
4 |
Open Source VHDL Reference Code for CNN research and development |
Nov 25, 2022 |
|
VHDL |
24 |
VHDL implementation of YAMAHA V9938 |
Aug 02, 2022 |
|
VHDL |
48 |
VHDL Implementation of AES Algorithm |
May 07, 2023 |
|
VHDL |
4 |
A VHDL implementation of VirtualWire/RadioHead |
Mar 04, 2021 |
|
VHDL |
2 |
Implementation of a CRC8 on VHDL |
Dec 13, 2020 |
|
VHDL |
2 |
Implementation of the CTG in VHDL |
Mar 26, 2023 |
|
VHDL |
2 |
Simple Cache Design Implementation in VHDL |
May 25, 2023 |
|
Jupyter Notebook |
2 |
Easily customizable implementation of Transfer Learning with Fine-Tuning using Keras pre-trained CNN models. |
Apr 21, 2023 |
|
VHDL |
3 |
TSEA43 |
Mar 16, 2017 |
|
VHDL |
4 |
None |
Jul 15, 2020 |
|
VHDL |
4 |
Design and implementation of a pipelined Bfloat16 Floating Point Arithmetic Unit using VHDL. This unit … |
Apr 18, 2022 |
|
VHDL |
4 |
None |
Apr 11, 2022 |
|
VHDL |
4 |
bnn accelerator |
Jan 12, 2022 |
|
VHDL |
4 |
基于MIPS指令集的cpu设计,能够通过龙芯杯个人赛测试。 |
Jul 02, 2022 |
|
VHDL |
4 |
None |
Jul 17, 2022 |
|
VHDL |
4 |
A smart speaker prototype for module 11 of Electrical Engineering at University of Twente |
Mar 04, 2021 |
|
VHDL |
4 |
CameraLink Gateway |
Apr 28, 2022 |
|
VHDL |
4 |
An 8-bit processor in VHDL based on a simple instruction set |
Jun 26, 2022 |
|
VHDL |
4 |
My HDL activities appear here. This is for my personal use. PPT's copyrights to University … |
Jul 20, 2022 |
|
VHDL |
4 |
My activities appear here,Copyrights to Colorado Boulder University-This is for personal use. |
Jun 03, 2022 |
|
VHDL |
4 |
A simple sprite example written in VHDL for DE10 Nano |
Mar 15, 2022 |
|
VHDL |
4 |
A simple tilemap example written in VHDL for DE10 Nano |
Mar 15, 2022 |
|
VHDL |
4 |
None |
Mar 18, 2022 |
|
VHDL |
4 |
None |
Jun 10, 2022 |
|
VHDL |
4 |
socz80 port for Altera FPGA boards |
Dec 04, 2018 |
|
VHDL |
4 |
None |
Apr 19, 2022 |
|
VHDL |
4 |
None |
Feb 14, 2021 |
|
VHDL |
4 |
Asteroids Deluxe |
Mar 11, 2022 |
|
VHDL |
4 |
Arcade games on Bally Astrocade Hardware |
Jan 19, 2022 |
|
VHDL |
4 |
Arcade: Crazy Kong for MiSTer |
Jun 10, 2021 |
|
VHDL |
4 |
Donkey Kong Junior |
Sep 22, 2021 |
|
VHDL |
4 |
Arcade: Pooyan for MiSTer |
Sep 29, 2021 |
|
VHDL |
4 |
FPGA implementation of Super Breakout arcade game released by Atari in 1978 |
May 20, 2022 |
|
VHDL |
4 |
Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details. |
Jul 27, 2021 |
|
VHDL |
4 |
None |
Jun 04, 2022 |
|
VHDL |
4 |
A floating-point streaming accelerator. |
Jan 11, 2022 |
|
VHDL |
4 |
Neural Turing Machine for a Processing Unit verified with UVM/OSVVM/FV |
Jul 21, 2022 |
|
VHDL |
4 |
Open FPGA Modules |
Jun 14, 2022 |
|
VHDL |
4 |
SCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption |
Aug 15, 2022 |
|
VHDL |
4 |
An AVR 2.x instructions set compatible CPU oriented to iCE40 FPGAs |
Oct 07, 2020 |
|
VHDL |
4 |
Integer (Scaled / Unscaled) Radix-2 Single Path Delay Feedback (SPDF) FFT / IFFT cores |
Apr 20, 2021 |
|
VHDL |
4 |
Develop the directors structure and testing infrastructure for CoreLib |
Mar 11, 2019 |
|
VHDL |
4 |
None |
Jul 06, 2020 |