|
Python |
2 |
A small library to communicate with AXI4 and AXI4-Stream hubs |
Mar 01, 2024 |
|
C++ |
47 |
SDRAM controller with AXI4 interface |
Mar 31, 2023 |
|
None |
3 |
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure |
Apr 19, 2022 |
|
SystemVerilog |
2 |
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure |
Jun 02, 2021 |
|
Elixir |
3 |
Use OpenID and OAuth with your Bonfire identity or connect to Bonfire with an external … |
Apr 18, 2023 |
|
OCaml |
13 |
Toplevel expectation test |
Nov 21, 2022 |
|
OCaml |
15 |
Javascript toplevel worker |
Apr 30, 2023 |
|
None |
2 |
Mbits axi4 avip |
Jun 21, 2023 |
|
CSS |
4 |
Bonfire website & blog |
Jun 25, 2022 |
|
HTML |
2 |
bonfire landing page |
Jun 30, 2021 |
|
TypeScript |
2 |
Bonfire - Scheduling dApp |
Apr 30, 2023 |
|
PHP |
4 |
Blog Bonfire Module |
Jun 22, 2015 |
|
OCaml |
758 |
Universal toplevel for OCaml |
Apr 30, 2023 |
|
SystemVerilog |
4 |
AXI4/AIB Bridge RTL |
Nov 07, 2022 |
|
OCaml |
4 |
Hide values starting with _ in the ocaml toplevel |
Nov 02, 2020 |
|
None |
5 |
Opam package with OCaml's native toplevel META file |
Apr 05, 2022 |
|
VHDL |
3 |
TSEA43 |
Mar 16, 2017 |
|
VHDL |
4 |
None |
Jul 15, 2020 |
|
VHDL |
4 |
Design and implementation of a pipelined Bfloat16 Floating Point Arithmetic Unit using VHDL. This unit … |
Apr 18, 2022 |
|
VHDL |
4 |
None |
Apr 11, 2022 |
|
VHDL |
4 |
bnn accelerator |
Jan 12, 2022 |
|
VHDL |
4 |
基于MIPS指令集的cpu设计,能够通过龙芯杯个人赛测试。 |
Jul 02, 2022 |
|
VHDL |
4 |
None |
Jul 17, 2022 |
|
VHDL |
4 |
A smart speaker prototype for module 11 of Electrical Engineering at University of Twente |
Mar 04, 2021 |
|
VHDL |
4 |
A VHDL implementation of VirtualWire/RadioHead |
Mar 04, 2021 |
|
VHDL |
4 |
CameraLink Gateway |
Apr 28, 2022 |
|
VHDL |
4 |
An 8-bit processor in VHDL based on a simple instruction set |
Jun 26, 2022 |
|
VHDL |
4 |
My HDL activities appear here. This is for my personal use. PPT's copyrights to University … |
Jul 20, 2022 |
|
VHDL |
4 |
My activities appear here,Copyrights to Colorado Boulder University-This is for personal use. |
Jun 03, 2022 |
|
VHDL |
4 |
A simple sprite example written in VHDL for DE10 Nano |
Mar 15, 2022 |
|
VHDL |
4 |
A simple tilemap example written in VHDL for DE10 Nano |
Mar 15, 2022 |
|
VHDL |
4 |
None |
Mar 18, 2022 |
|
VHDL |
4 |
None |
Jun 10, 2022 |
|
VHDL |
4 |
socz80 port for Altera FPGA boards |
Dec 04, 2018 |
|
VHDL |
4 |
None |
Apr 19, 2022 |
|
VHDL |
4 |
None |
Feb 14, 2021 |
|
VHDL |
4 |
Asteroids Deluxe |
Mar 11, 2022 |
|
VHDL |
4 |
Arcade games on Bally Astrocade Hardware |
Jan 19, 2022 |
|
VHDL |
4 |
Arcade: Crazy Kong for MiSTer |
Jun 10, 2021 |
|
VHDL |
4 |
Donkey Kong Junior |
Sep 22, 2021 |
|
VHDL |
4 |
Arcade: Pooyan for MiSTer |
Sep 29, 2021 |
|
VHDL |
4 |
FPGA implementation of Super Breakout arcade game released by Atari in 1978 |
May 20, 2022 |
|
VHDL |
4 |
Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details. |
Jul 27, 2021 |
|
VHDL |
4 |
None |
Jun 04, 2022 |
|
VHDL |
4 |
A floating-point streaming accelerator. |
Jan 11, 2022 |
|
VHDL |
4 |
Neural Turing Machine for a Processing Unit verified with UVM/OSVVM/FV |
Jul 21, 2022 |
|
VHDL |
4 |
Open FPGA Modules |
Jun 14, 2022 |
|
VHDL |
4 |
SCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption |
Aug 15, 2022 |
|
VHDL |
4 |
An AVR 2.x instructions set compatible CPU oriented to iCE40 FPGAs |
Oct 07, 2020 |
|
VHDL |
4 |
Integer (Scaled / Unscaled) Radix-2 Single Path Delay Feedback (SPDF) FFT / IFFT cores |
Apr 20, 2021 |