|
Assembly |
13 |
The Commodore TED (C16, C116, Plus/4) KERNAL, buildable with cc65 |
May 01, 2023 |
|
Verilog |
10 |
Commodore PET for MiSTer |
Jul 23, 2022 |
|
C# |
11 |
Terminal 6502 Emulator with Commodore 64, 128, Vic-20, PET 2001, and TED: C16, Plus/4 |
May 05, 2022 |
|
VHDL |
10 |
Commodore VIC-20 for MiSTer |
Jun 06, 2022 |
|
CoffeeScript |
4 |
A HTML5 recreation of the Commodore C16 game |
Sep 09, 2020 |
|
SystemVerilog |
27 |
Macintosh Plus for MiSTer |
Mar 09, 2022 |
|
C++ |
206 |
Sidekick64: A Versatile Software-Defined Cartridge for the C64, C128, C16, plus/4, and VIC20 |
Jun 01, 2023 |
|
None |
2 |
Parallel Port Adapter for the Commodore Plus/4 |
Apr 08, 2023 |
|
JavaScript |
16 |
A Commodore 64 & Commodore Plus/4 pixel editor made in HTML5/JS |
Jul 27, 2022 |
|
JavaScript |
3 |
A Commodore 64 & Commodore Plus/4 pixel editor made in HTML5/JS |
Jan 28, 2023 |
|
Pawn |
6 |
User Port Cartridge for the Commodore 16, 116 and Plus/4 |
Jan 23, 2023 |
|
VHDL |
11 |
Commodore 64 core for the MEGA65 based on the MiSTer FPGA C64 core |
Jun 28, 2022 |
|
None |
2 |
RS-232 Serial Port Adapter for the Commodore Plus/4 |
Aug 25, 2023 |
|
Assembly |
60 |
A patch for Commodore 64 and Plus/4 Elite that removes the flicker |
Apr 22, 2023 |
|
Verilog |
5 |
C16/Plus4 core |
Sep 01, 2022 |
|
SystemVerilog |
4 |
Moving Average |
Jan 28, 2022 |
|
SystemVerilog |
4 |
Collaborative project to create an advanced GPU for the Microcom computer. |
Jun 12, 2022 |
|
SystemVerilog |
4 |
SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 … |
May 25, 2022 |
|
SystemVerilog |
4 |
This example .BMP generator and ASCII script file reader can be adapted to test code … |
May 25, 2022 |
|
SystemVerilog |
4 |
FPGA low latency 10GBASE-R PCS |
May 19, 2022 |
|
SystemVerilog |
4 |
A continually growing system verilog parts library |
Dec 09, 2021 |
|
SystemVerilog |
4 |
基于FPGA的CNN图像分类系统 |
May 06, 2022 |
|
SystemVerilog |
4 |
Intel CPU Garage Challenge |
Jun 13, 2022 |
|
SystemVerilog |
4 |
system verilog course labs |
Nov 09, 2021 |
|
SystemVerilog |
4 |
Hardware-Software codesign project. |
Dec 12, 2021 |
|
SystemVerilog |
4 |
Verilog code for a simple synth module; developed on TinyFPGA BX |
Jul 18, 2022 |
verilator-dynamic-scheduler-tests
|
SystemVerilog |
4 |
None |
Mar 04, 2022 |
|
SystemVerilog |
4 |
まともなRISC-V CPU |
Jul 18, 2022 |
|
SystemVerilog |
4 |
Goal: Write an even higher performing solution generator |
Feb 22, 2021 |
|
SystemVerilog |
4 |
Verification IP for APB protocol |
Jul 30, 2022 |
|
SystemVerilog |
4 |
None |
Aug 07, 2022 |
|
SystemVerilog |
4 |
None |
Jan 21, 2022 |
|
SystemVerilog |
4 |
RISC-V Core Local Interrupt Controller (CLINT) |
Jul 14, 2022 |
|
SystemVerilog |
4 |
None |
Feb 17, 2022 |
|
SystemVerilog |
4 |
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs |
Feb 07, 2022 |
|
SystemVerilog |
4 |
Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores |
Jun 15, 2022 |
|
SystemVerilog |
4 |
Neural Engine, 16 input channels |
Jul 18, 2022 |
|
SystemVerilog |
4 |
None |
Jun 29, 2022 |
|
SystemVerilog |
4 |
None |
Mar 30, 2022 |
|
SystemVerilog |
4 |
None |
Jun 05, 2022 |
|
SystemVerilog |
4 |
None |
Sep 17, 2020 |
|
SystemVerilog |
4 |
A simulated memory controller for use in FPGA designs that want to model real system … |
Jul 12, 2021 |
|
SystemVerilog |
4 |
Financial Technology with SoC-NTM verified with UVM/OSVVM/FV |
Jul 19, 2022 |
|
SystemVerilog |
4 |
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA) |
Aug 06, 2022 |
|
SystemVerilog |
4 |
RISC-V assembler/dis-assembler written in SystemVerilog |
Nov 18, 2020 |
|
SystemVerilog |
5 |
🎓 Repositório com as atividades desenvolvidas ao longo da disciplina de laboratório de organização e … |
Jun 01, 2022 |
|
SystemVerilog |
5 |
8086-compatible cpu |
May 06, 2022 |
|
SystemVerilog |
5 |
SPIで制御出来るアクセラレータ |
Nov 17, 2021 |
|
SystemVerilog |
5 |
Verification IP for SPI protocol |
Jul 30, 2022 |
|
SystemVerilog |
5 |
A chisel3 wrapper for pulp-platform/fpnew |
Aug 01, 2020 |