|
Verilog |
2 |
Ultratank core for MiSTer |
Nov 19, 2021 |
|
Verilog |
2 |
BankPanic FPGA core for MiSTer |
Oct 07, 2022 |
|
VHDL |
3 |
Rygar (1986) core for MiSTer |
Jun 16, 2020 |
|
Verilog |
3 |
CoCo2 / Dragon Core for MiSTer |
Dec 02, 2021 |
|
Verilog |
8 |
Amstrad PCW MiSTer core |
Jun 02, 2022 |
|
VHDL |
5 |
Mario Bros arcade core for MiSTer |
Sep 26, 2021 |
|
C++ |
5 |
Input test utility core for MiSTer |
Jul 22, 2022 |
|
VHDL |
2 |
Ondra SPO 186 core for MISTer |
Oct 31, 2022 |
|
Verilog |
2 |
Fairchild Channel F core for MiSTer |
Nov 02, 2021 |
|
Verilog |
2 |
RX-78 core for MiSTer FPGA |
Mar 14, 2022 |
|
Verilog |
3 |
Orao FPGA core implementation for MiSTer |
Jan 01, 2021 |
|
Verilog |
5 |
Slap Fight MiSTer FPGA Core |
Jan 13, 2023 |
|
Verilog |
51 |
SNK NeoGeo core for the MiSTer platform |
Mar 25, 2022 |
|
Verilog |
2 |
MiSTer arcade core for Sega's Dottori-Kun |
Sep 12, 2023 |
|
Verilog |
9 |
Arduboy core for MiSTer, based on Iulian Gheorghiu's atmega core. |
Mar 01, 2022 |
|
C++ |
2 |
VTECH Laser 310 Mister FPGA core |
Apr 06, 2023 |
|
VHDL |
2 |
Tomy Tutor/Pyuta/Pyuta Jr. Core for MiSTer |
Jan 19, 2023 |
|
Scala |
64 |
MiSTer arcade core for Cave 68K arcade classics. |
Aug 04, 2022 |
|
C# |
2 |
Utility for Rom injection into Rbf core for MiSTer |
Jul 20, 2023 |
|
VHDL |
11 |
Commodore 64 core for the MEGA65 based on the MiSTer FPGA C64 core |
Jun 28, 2022 |
|
None |
31 |
FPGA compatible core for the Nemesis (1985) arcade hardware for MiSTer FPGA. |
Apr 20, 2022 |
|
Shell |
2 |
Scripts and tasks for keeping MiSTer core forks synced with their upstreams. |
Dec 08, 2021 |
|
VHDL |
4 |
Arcade: Galaga for the MEGA65, based on the original MiSTer Galaga core. |
Nov 19, 2023 |
|
Verilog |
5 |
ZX81 for MiSTer |
Feb 16, 2022 |
|
VHDL |
7 |
ColecoVision for MiSTer |
Feb 13, 2022 |
|
VHDL |
10 |
Vectrex for MiSTer |
Mar 01, 2022 |
|
VHDL |
11 |
Intellivision for MiSTer |
Jul 18, 2022 |
|
Verilog |
2 |
Gaplus for MiSTer |
Jan 29, 2022 |
|
VHDL |
2 |
Gyruss for MiSTer |
May 27, 2022 |
|
VHDL |
2 |
GBA for MiSTer |
Dec 06, 2021 |
|
Verilog |
2 |
NeoGeo for MiSTer |
Jan 17, 2022 |
|
VHDL |
2 |
SNES for MiSTer |
Jan 05, 2022 |
|
VHDL |
15 |
SNES for MiSTer |
May 11, 2021 |
|
VHDL |
26 |
MSX for MiSTer |
Jun 27, 2022 |
|
Python |
27 |
Fonts for MiSTer |
May 23, 2022 |
|
VHDL |
50 |
PSX for MiSTer |
Aug 11, 2022 |
|
Verilog |
76 |
Gameboy for MiSTer |
Aug 01, 2022 |
|
Verilog |
103 |
NeoGeo for MiSTer |
Aug 20, 2022 |
|
VHDL |
107 |
GBA for MiSTer |
Jul 05, 2022 |
|
VHDL |
111 |
PSX for MiSTer |
Jul 31, 2022 |
|
VHDL |
137 |
SNES for MiSTer |
Aug 10, 2022 |
|
Verilog |
3 |
NeoGeo for MiSTer |
Mar 25, 2022 |
|
Verilog |
5 |
Gameboy for MiSTer |
May 26, 2022 |
|
VHDL |
4 |
PSX for MiSTer |
May 21, 2023 |
|
Python |
4 |
Rom utilities for the TI-99/4a core of the MiSter FPGA project |
Aug 23, 2021 |
|
Verilog |
3 |
SJTU CS145 Computer Architecture Labs. |
Apr 08, 2022 |
|
Verilog |
4 |
This is the design experiment of a third-year computer composition principle course in a university. … |
Mar 15, 2021 |
|
Verilog |
4 |
Skywater 130nm LDO parts and DPLL |
May 03, 2022 |
|
Verilog |
4 |
None |
Apr 11, 2022 |
|
Verilog |
4 |
[DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs |
Mar 27, 2022 |