Stars
14
Forks
5
Language
C++
Last Updated
Dec 16, 2023
Similar Repos
Repo | Language | Stars | Description | Updated At |
---|---|---|---|---|
C++ | 3 | vivado hls | Aug 20, 2021 | |
VHDL | 8 | Vivado HLS implementation of EDFLOW IP | Sep 04, 2022 | |
C | 3 | Vivado HLS for prime testing | Aug 31, 2019 | |
Jupyter Notebook | 22 | Contains FPGA benchmarks for Vivado HLS and Catapult HLS | Dec 09, 2022 | |
VHDL | 2 | A Demo Project for Vivado HLS. | Jan 30, 2021 | |
Tcl | 2 | Getting started with Vivado and PetaLinux with Zynq EBAZ4205 Board | Apr 10, 2023 | |
Tcl | 10 | Huffman encoding core (Vivado HLS) | Apr 28, 2023 | |
C++ | 5 | Implementation of time and space-tiled stencil in Vivado HLS. | Mar 15, 2022 | |
Tcl | 3 | An implementation of MD5 algorithm on FPGA using Vivado HLS | Sep 29, 2021 | |
None | 2 | FPGA implementation of Canny edge detection by using Vivado HLS | May 06, 2023 | |
Python | 3 | Realtime 3D Rendering with Vivado HLS on Zedboard | Nov 12, 2022 | |
C | 4 | An implementation of SZ lossy compression in Vivado HLS for Xilinx FPGAs. | Jul 31, 2022 | |
C++ | 3 | QPSK system implemented using Vivado HLS | May 01, 2021 | |
C++ | 6 | Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms. | Mar 15, 2022 | |
Python | 34 | A Vivado HLS Command Line Helper Tool | Mar 22, 2022 | |
C | 4 | hardware accelerator for sha256 hash algorithm using Vivado HLS | Mar 05, 2023 | |
VHDL | 8 | This is a Vivado project to create an IoT device with ZYBO (Zynq). | Sep 15, 2022 | |
Jupyter Notebook | 20 | Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for … | May 04, 2023 | |
None | 3 | AES-128 CTR mode Encryption/Decryption system for Vivado HLS | Nov 02, 2021 | |
TeX | 3 | IIR digital filter implemented using Vivado HLS and C++ | Mar 13, 2022 | |
C++ | 14 | A C++ template library for FPGAs on top of Xilinx Vivado HLS | Jul 15, 2021 | |
C++ | 14 | A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS | Mar 13, 2023 | |
C++ | 2 | A repo containing some of my code from Xilinx Vivado HLS tool. | Jul 24, 2022 | |
C++ | 207 | Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs. | Jul 28, 2022 | |
C++ | 102 | [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS. | Apr 26, 2023 | |
C++ | 9 | CUDA Implementation of the Heston Model for Option Pricing | Jun 14, 2022 | |
Dockerfile | 23 | Dockerfile with Vivado for CI | Dec 02, 2022 | |
Verilog | 3 | Simple project demonstrating a method of interfacing the Opal Kelly FrontPanel interface with a Vivado … | Jan 28, 2023 | |
Python | 93 | [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs. | Apr 26, 2023 | |
None | 2 | [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs. | May 04, 2023 | |
Java | 7 | ExoPlayer HLS simple implementation | May 04, 2016 | |
Jupyter Notebook | 13 | A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC | Apr 18, 2023 | |
Python | 17 | HLS server implementation in python | Nov 04, 2022 | |
Verilog | 2 | Portable Mandelbrot Set with ZYBO (Zynq) | Apr 02, 2023 | |
Jupyter Notebook | 1497 | Python Productivity for ZYNQ | Aug 12, 2022 | |
None | 2 | Python Productivity for ZYNQ | May 25, 2022 | |
C++ | 4 | Intel HLS Implementation of Convolutional Neural Networks for FPGAs | Sep 07, 2021 | |
C++ | 7 | Source codes for High Level Synthesis for Fixed Progammable Gate Arrays (FPGAs). Can be converted … | Dec 19, 2021 | |
BitBake | 5 | Yocto recipes for machine learning libraries (mainly for Zynq-7000 & Zynq MPSoC devices) | May 20, 2022 | |
VHDL | 41 | Open source Zynq timestamping implementation from Software Radio Systems (SRS) | Apr 24, 2023 | |
None | 2 | Open source Zynq timestamping implementation from Software Radio Systems (SRS) | Oct 31, 2023 | |
Verilog | 4 | Stopwatch ⏱️ implemented using Verilog with Vivado | May 21, 2023 | |
Makefile | 8 | Template design and boot image for ZYNQ and ZYNQ Ultrascale+ Development Boards | May 04, 2022 | |
None | 5 | 🧛🏻♂️ Dark theme for Vivado | May 02, 2022 | |
Python | 15 | Bazel rules for Xilinx Vivado | Apr 19, 2023 | |
Verilog | 3 | Firmware for the SM Zynq | Jan 14, 2023 | |
VHDL | 18 | Vivado design for basic NeTV2 FPGA with chroma-based overlay | Jun 10, 2022 | |
TypeScript | 58 | Free live streaming with Free-HLS (Free HLS 直播姬) | Aug 09, 2022 | |
Verilog | 2 | Vivado project with example of simple 4bit CPU | Aug 17, 2019 | |
Verilog | 4 | Designs and problems in verilog language with vivado. | Feb 28, 2023 |