|
Verilog |
6 |
Chroma key IP block for NeTV2 |
Jan 29, 2022 |
|
C |
5 |
FPGA code for NeTV2 |
May 08, 2021 |
|
C |
5 |
FPGA code for NeTV2 |
Feb 05, 2023 |
|
Tcl |
7 |
HDMI/DVI decoder for NeTV2 FPGA |
Jan 29, 2022 |
|
Verilog |
5 |
DVI encoder block for NeTV2 FPGA |
Jan 29, 2022 |
|
Verilog |
13 |
HDCP cipher engine for the NeTV2 FPGA |
May 09, 2023 |
|
Jupyter Notebook |
20 |
Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for … |
May 04, 2023 |
|
Java |
203 |
Build Customized FPGA Implementations for Vivado |
Aug 17, 2022 |
|
Tcl |
37 |
Sample minimal Vivado project for Parallella FPGA |
Dec 15, 2022 |
|
Shell |
2 |
Gentoo overlay with ebuilds for FPGA toolchains. |
Mar 30, 2023 |
|
Tcl |
8 |
NeTV2 FPGA snooper for the HDCP block transfer across the DDC |
Jan 29, 2022 |
|
Jupyter Notebook |
22 |
Contains FPGA benchmarks for Vivado HLS and Catapult HLS |
Dec 09, 2022 |
|
Tcl |
37 |
A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite |
Aug 15, 2022 |
|
VHDL |
2 |
Collection of gen3 readout FPGA blocks and submodules for Vivado |
Sep 16, 2021 |
|
Tcl |
2 |
ELEC2665 / XJEL2665 FPGA coursework. Design of an FPGA-based stopwatch. |
Jul 30, 2022 |
|
GLSL |
19 |
FPGA design sources for ATOM Display FPGA |
May 04, 2023 |
|
Python |
5 |
buildsystem for for HWToolkit (fpga devel. tools), Vivado, Modelsim, Quartus, Yosys etc. |
Jan 16, 2023 |
|
Python |
218 |
FPGA Design Suite based on C to Verilog design flow. |
Oct 18, 2022 |
|
Verilog |
2 |
FPGA设计,借助Vivado和Ego1实验平台设计的密码锁【内附报告】(FPGA design, password lock designed by vivado and ego1 experimental platform [attached report]) |
Oct 19, 2022 |
|
C |
462 |
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro |
Apr 27, 2023 |
|
C |
2 |
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro |
Apr 11, 2023 |
|
None |
2 |
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro |
Jun 19, 2023 |
|
C |
15 |
The FPGA design for the FreeSRP's Artix 7 FPGA |
Nov 10, 2022 |
|
Dockerfile |
23 |
Dockerfile with Vivado for CI |
Dec 02, 2022 |
|
Python |
2 |
FPGA development board (DE1) targetted lm32 based systems design for Verilog |
Mar 08, 2023 |
|
C++ |
102 |
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS. |
Apr 26, 2023 |
|
TypeScript |
4 |
Basic FPGA programming extension for vscode |
Nov 10, 2022 |
|
C |
44 |
FPGA GPU design for DE1-SoC |
Jul 31, 2022 |
|
None |
3 |
FPGA Design for the ebaz4205 board. |
Oct 04, 2022 |
|
Tcl |
22 |
FPGA Design for the ebaz4205 board. |
May 04, 2023 |
|
Jupyter Notebook |
8 |
implement convolution neural network on FPGA based on VHDL design |
Apr 01, 2023 |
|
JavaScript |
4 |
Basic overlay module written for easy customization |
Jan 12, 2021 |
|
JavaScript |
2 |
A basic feedback overlay for question components |
Feb 21, 2023 |
|
PHP |
13 |
Twitch web-based Overlay with Laravel |
Oct 24, 2022 |
|
None |
14 |
BaseBoard design for QMTech Kintex 7 FPGA |
Mar 19, 2023 |
|
Verilog |
115 |
An open source FPGA design for DSLogic |
Apr 24, 2023 |
|
None |
5 |
Design files for FPGA1394 board (FPGA + FireWire) |
Jan 29, 2023 |
|
C++ |
13 |
Heston implementation for Zynq with Vivado HLS |
May 06, 2022 |
|
C |
109 |
FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC) |
Apr 11, 2023 |
|
Python |
3 |
A Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and … |
Oct 16, 2023 |
|
Python |
2 |
API wrapper for communication with Razer Chroma devices |
Apr 22, 2023 |
|
VHDL |
3 |
TSEA43 |
Mar 16, 2017 |
|
VHDL |
4 |
None |
Jul 15, 2020 |
|
VHDL |
4 |
Design and implementation of a pipelined Bfloat16 Floating Point Arithmetic Unit using VHDL. This unit … |
Apr 18, 2022 |
|
VHDL |
4 |
None |
Apr 11, 2022 |
|
VHDL |
4 |
bnn accelerator |
Jan 12, 2022 |
|
VHDL |
4 |
基于MIPS指令集的cpu设计,能够通过龙芯杯个人赛测试。 |
Jul 02, 2022 |
|
VHDL |
4 |
None |
Jul 17, 2022 |
|
VHDL |
4 |
A smart speaker prototype for module 11 of Electrical Engineering at University of Twente |
Mar 04, 2021 |
|
VHDL |
4 |
A VHDL implementation of VirtualWire/RadioHead |
Mar 04, 2021 |