|
Python |
3 |
NaxRiscv integration test with LiteX |
Jun 17, 2022 |
|
Verilog |
23 |
VexRiscv-SMP integration test with LiteX. |
Mar 01, 2022 |
|
Python |
9 |
HBM2 integration test on FK33 with LiteX |
Apr 19, 2022 |
|
Python |
6 |
Integration test with SpinalHDL's OHCI USB Host core and LiteX/VexRiscv-SMP. |
May 15, 2022 |
|
Python |
5 |
Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX. |
Jul 19, 2022 |
|
VHDL |
2 |
A test audio processor using the NEORV32 |
Aug 02, 2022 |
|
Python |
10 |
LiteX LUNA USB stack integration |
Aug 02, 2022 |
|
Python |
3 |
Test of LiteX standalone SoC generator. |
Jun 28, 2022 |
|
Verilog |
6 |
Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities. |
Mar 11, 2023 |
|
TypeScript |
2 |
integration with Test Rail |
Mar 03, 2023 |
|
Python |
6 |
Test of a RP2040 PMOD attached to a LiteX SoC. |
Oct 20, 2022 |
|
None |
2 |
RISC-V (NEORV32) on CYC1000 |
Apr 16, 2022 |
|
Verilog |
2 |
Experiment with LiteX on proFPGA systems |
Oct 22, 2021 |
|
VHDL |
3 |
TSEA43 |
Mar 16, 2017 |
|
VHDL |
4 |
None |
Jul 15, 2020 |
|
VHDL |
4 |
Design and implementation of a pipelined Bfloat16 Floating Point Arithmetic Unit using VHDL. This unit … |
Apr 18, 2022 |
|
VHDL |
4 |
None |
Apr 11, 2022 |
|
VHDL |
4 |
bnn accelerator |
Jan 12, 2022 |
|
VHDL |
4 |
基于MIPS指令集的cpu设计,能够通过龙芯杯个人赛测试。 |
Jul 02, 2022 |
|
VHDL |
4 |
None |
Jul 17, 2022 |
|
VHDL |
4 |
A smart speaker prototype for module 11 of Electrical Engineering at University of Twente |
Mar 04, 2021 |
|
VHDL |
4 |
A VHDL implementation of VirtualWire/RadioHead |
Mar 04, 2021 |
|
VHDL |
4 |
CameraLink Gateway |
Apr 28, 2022 |
|
VHDL |
4 |
An 8-bit processor in VHDL based on a simple instruction set |
Jun 26, 2022 |
|
VHDL |
4 |
My HDL activities appear here. This is for my personal use. PPT's copyrights to University … |
Jul 20, 2022 |
|
VHDL |
4 |
My activities appear here,Copyrights to Colorado Boulder University-This is for personal use. |
Jun 03, 2022 |
|
VHDL |
4 |
A simple sprite example written in VHDL for DE10 Nano |
Mar 15, 2022 |
|
VHDL |
4 |
A simple tilemap example written in VHDL for DE10 Nano |
Mar 15, 2022 |
|
VHDL |
4 |
None |
Mar 18, 2022 |
|
VHDL |
4 |
None |
Jun 10, 2022 |
|
VHDL |
4 |
socz80 port for Altera FPGA boards |
Dec 04, 2018 |
|
VHDL |
4 |
None |
Apr 19, 2022 |
|
VHDL |
4 |
None |
Feb 14, 2021 |
|
VHDL |
4 |
Asteroids Deluxe |
Mar 11, 2022 |
|
VHDL |
4 |
Arcade games on Bally Astrocade Hardware |
Jan 19, 2022 |
|
VHDL |
4 |
Arcade: Crazy Kong for MiSTer |
Jun 10, 2021 |
|
VHDL |
4 |
Donkey Kong Junior |
Sep 22, 2021 |
|
VHDL |
4 |
Arcade: Pooyan for MiSTer |
Sep 29, 2021 |
|
VHDL |
4 |
FPGA implementation of Super Breakout arcade game released by Atari in 1978 |
May 20, 2022 |
|
VHDL |
4 |
Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details. |
Jul 27, 2021 |
|
VHDL |
4 |
None |
Jun 04, 2022 |
|
VHDL |
4 |
A floating-point streaming accelerator. |
Jan 11, 2022 |
|
VHDL |
4 |
Neural Turing Machine for a Processing Unit verified with UVM/OSVVM/FV |
Jul 21, 2022 |
|
VHDL |
4 |
Open FPGA Modules |
Jun 14, 2022 |
|
VHDL |
4 |
SCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption |
Aug 15, 2022 |
|
VHDL |
4 |
An AVR 2.x instructions set compatible CPU oriented to iCE40 FPGAs |
Oct 07, 2020 |
|
VHDL |
4 |
Integer (Scaled / Unscaled) Radix-2 Single Path Delay Feedback (SPDF) FFT / IFFT cores |
Apr 20, 2021 |
|
VHDL |
4 |
Develop the directors structure and testing infrastructure for CoreLib |
Mar 11, 2019 |
|
VHDL |
4 |
None |
Jul 06, 2020 |
|
VHDL |
4 |
A transformable CPU, one version using FPGA technology and another using an ARM Cortex-M4 (K64F) … |
May 20, 2022 |