|
VHDL |
4 |
⚙️ IP Cores for Xilinx FPGA Devices |
Jan 07, 2020 |
|
VHDL |
15 |
Agile Network Tester with FPGA & multi-cores |
Apr 27, 2022 |
|
Tcl |
7 |
Repository for FPGA projects |
Mar 20, 2023 |
|
Tcl |
87 |
SDK for FPGA / Linux Instruments |
May 18, 2023 |
|
None |
13 |
Information on cores available on the Ulx3s ECP5 FPGA board |
Jul 18, 2022 |
|
VHDL |
2 |
Misc. FPGA Projects |
May 24, 2023 |
|
Verilog |
2 |
My projects for ULX3S FPGA |
Nov 13, 2019 |
|
Shell |
43 |
Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety … |
Jul 29, 2022 |
|
Python |
26 |
My pergola FPGA projects |
Mar 17, 2022 |
|
SMT |
5 |
Internal Logic Analyser for FPGA Projects |
Jun 05, 2022 |
|
Verilog |
7 |
FPGA shared code for my projects |
Nov 18, 2022 |
|
VHDL |
11 |
Projects for the Scarab Minispartan6+ FPGA board |
Feb 16, 2023 |
|
Verilog |
5 |
Intro to FPGA class projects |
Jan 30, 2022 |
|
Java |
145 |
Java-based projects using the HERE SDK for Android. |
Apr 27, 2023 |
|
Shell |
3 |
Truffle cores running on large public Truffle projects. |
Sep 05, 2018 |
|
Verilog |
71 |
FPGA based transmitter |
Aug 17, 2022 |
|
SystemVerilog |
15 |
🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol) |
Mar 22, 2023 |
|
VHDL |
2 |
Memory IP cores, mainly oriented to memories that map to FPGA embedded memories |
May 24, 2024 |
|
VHDL |
2 |
Repository containing a fork of wr-cores available here: http://www.ohwr.org/projects/wr-cores/repository |
Mar 22, 2023 |
|
Verilog |
5 |
FPGA project based on Xilinx FPGA EGO1 xc7a35tcsg324 |
Nov 29, 2022 |
|
Verilog |
6 |
Test projects for the OrangeCrab ECP5 FPGA board |
May 12, 2022 |
|
C |
38 |
repository for Vidor FPGA IP blocks and projects |
Mar 15, 2023 |
|
SystemVerilog |
2 |
NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board |
Oct 24, 2022 |
|
Python |
10 |
LiteX based FPGA gateware for Thunderscope. |
Aug 11, 2022 |
|
Verilog |
2 |
FPGA based VGA output for Gameboys |
Feb 09, 2023 |
|
Python |
5 |
FPGA based fractional resampler |
Jul 30, 2022 |
|
VHDL |
8 |
FPGA-based data partitioning |
May 25, 2022 |
|
None |
10 |
FPGA-based Eink Controller |
Jun 09, 2022 |
|
C++ |
11 |
FPGA-based HyperLogLog Accelerator |
Apr 02, 2022 |
|
VHDL |
58 |
image processing based FPGA |
May 08, 2023 |
|
VHDL |
14 |
fpga based nes box |
Mar 16, 2023 |
|
Verilog |
10 |
This repository contains FPGA code for various projects like Lighthouse Tracking as well as some … |
Sep 11, 2022 |
|
SystemVerilog |
44 |
FPGA IP cores for the Antikernel OS, intended to be included as a submodule in … |
Mar 16, 2023 |
|
Verilog |
2 |
FPGA based Logic analyzer designed then FPGA implemented on ALTERA cyclone IV FPGA |
May 09, 2024 |
|
None |
2 |
Cores for Server. |
Jun 22, 2022 |
|
Verilog |
10 |
Projects for the ECPiX-5 - a ECP5 FPGA board. |
Mar 18, 2022 |
|
VHDL |
15 |
Various projects of SPI loader module for xilinx fpga |
Apr 24, 2023 |
|
Verilog |
6 |
Some buggy FPGA projects written by Verilog. |
Feb 24, 2022 |
|
SystemVerilog |
2 |
FPGA design elements used across multiple projects. |
Dec 21, 2023 |
|
Verilog |
3 |
SJTU CS145 Computer Architecture Labs. |
Apr 08, 2022 |
|
Verilog |
4 |
This is the design experiment of a third-year computer composition principle course in a university. … |
Mar 15, 2021 |
|
Verilog |
4 |
Skywater 130nm LDO parts and DPLL |
May 03, 2022 |
|
Verilog |
4 |
None |
Apr 11, 2022 |
|
Verilog |
4 |
[DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs |
Mar 27, 2022 |
|
Verilog |
4 |
UVM Testbench for Keccak sha3 core downloaded from Opencores https://opencores.org/projects/sha3 |
Mar 30, 2022 |
|
Verilog |
4 |
None |
Jun 02, 2022 |
|
Verilog |
4 |
Comprehensive hardware library in Verilog for hardware primitives |
Oct 30, 2021 |
|
Verilog |
4 |
Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor … |
May 25, 2022 |
|
Verilog |
4 |
None |
Jun 07, 2022 |
|
Verilog |
4 |
None |
Jan 04, 2022 |