|
Verilog |
2 |
A hardened macro with sky130B PDK of slightly modified zero-riscy RISC-V core |
Dec 10, 2023 |
|
SystemVerilog |
787 |
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. |
Aug 12, 2022 |
|
None |
2 |
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. |
Aug 23, 2021 |
|
None |
2 |
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. |
May 17, 2021 |
|
Bluespec |
13 |
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT |
Apr 21, 2023 |
|
Verilog |
14 |
Dual-core RISC-V SoC with JTAG, atomics, SDRAM |
Aug 02, 2022 |
|
SystemVerilog |
2 |
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, … |
Jul 22, 2022 |
|
C++ |
6 |
Play and learn with the SiFive HiFive1 board featuring a FE310-G000 SoC integrating SiFive's E31 … |
May 04, 2023 |
|
Verilog |
122 |
A 32-bit Microcontroller featuring a RISC-V core |
Jul 17, 2022 |
|
None |
3 |
L6 R5:RISC-V 400MHz Dual Core AIoT 0.2TOPS SoC (K210) |
Dec 09, 2022 |
|
None |
2 |
L7 R5:RISC-V 800MHz Dual Core AIoT (2.5TOPS) SoC (K510) |
Sep 02, 2022 |
|
Verilog |
63 |
Basic RISC-V Test SoC |
Apr 22, 2023 |
|
SystemVerilog |
7 |
[Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core. |
Feb 24, 2023 |
|
VHDL |
374 |
A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz |
May 11, 2023 |
|
None |
614 |
RISC-V Cores, SoC platforms and SoCs |
Jul 15, 2022 |
|
None |
5 |
L2:WCH 120MHz RISC-V3A SoC (CH565) |
Nov 11, 2022 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Sep 07, 2021 |
|
None |
3 |
RISC-V Cores, SoC platforms and SoCs |
Apr 14, 2023 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Dec 06, 2022 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Apr 19, 2022 |
|
None |
3 |
RISC-V Cores, SoC platforms and SoCs |
Jan 07, 2023 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Mar 14, 2024 |
|
Scala |
1040 |
RISC-V SoC designed by students in UCAS |
Aug 06, 2022 |
|
C |
2 |
Linux Kernel Source for Sophgo RISC-V SoC |
Mar 18, 2023 |
|
Rust |
9 |
Rust examples for RISC Zero |
Jun 17, 2022 |
|
Rust |
2 |
Using Rust on a customized LiteX SoC (RISC-V). |
Mar 21, 2023 |
|
C |
14 |
L2 R6: WCH 120MHz RISC-V3A USB3.0 SoC (CH569) |
Feb 18, 2023 |
|
C |
9 |
L2 R2: WCH RISC-V BLE SoC (CH573/CH571) |
Mar 20, 2023 |
|
C |
2 |
L2 R2:WCH 144MHz RISC-V4C BLE SoC(CH32V208) |
Apr 27, 2023 |
|
None |
3 |
L4 R4:32-bit RISC-V WiFi + BT SoC |
Dec 15, 2023 |
|
Rust |
3 |
Use RISC Zero to check Metamath |
Apr 25, 2023 |
|
C |
2 |
SOPHGO RISC-V Zero Stage BootLoader |
Jul 08, 2023 |
|
SystemVerilog |
229 |
RISC-V CPU Core |
Apr 22, 2023 |
|
Rust |
4 |
rusty-riscy is a performance testing and benchmarking tool for RISC-V processors written in Rust. |
Apr 08, 2023 |
|
Rust |
13 |
RISC Zero Nova is inherit from Risc Zero but aim to replace STARK with Nova … |
Jul 22, 2023 |
|
Verilog |
9 |
RISC-V SoC designed for the Efabless Open MPW Program |
Sep 21, 2022 |
|
Python |
8 |
RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator |
Dec 31, 2021 |
|
Verilog |
3 |
A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 … |
Jan 06, 2023 |
|
None |
3 |
RISC-V Core Test Framework |
Feb 08, 2023 |
|
Verilog |
773 |
RISC-V CPU Core (RV32IM) |
Apr 23, 2023 |
|
None |
2 |
RISC-V CPU Core (RV32IM) |
Dec 12, 2021 |
|
Haskell |
2 |
Functionally described RISC-V core |
Jan 04, 2020 |
|
C |
10 |
L2 R2:WCH 80MHz RISC-V4A BLE SoC (CH583/CH582/CH581) |
Mar 09, 2023 |
|
None |
2 |
Hardware abstraction level (HAL) for HiSilicon Hi3861 RISC-V Radio SoC |
Oct 30, 2020 |
|
Python |
2 |
MicroPython auf SiPEED M1 Modules incl. Kendryte K210 RISC-V SoC |
Sep 17, 2021 |
|
Verilog |
50 |
A small SoC with a pipeline 32-bit RISC-V CPU. |
May 10, 2023 |
|
C |
149 |
Tiny FEL tools for allwinner SOC, support RISC-V D1 chip |
Apr 25, 2023 |
|
C |
7 |
Framework for writing directed diags for RISC-V CPU/SOC validation. |
Oct 12, 2023 |
|
Rust |
518 |
RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V … |
Aug 30, 2022 |
|
None |
3 |
A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL. |
Jul 07, 2021 |