|
None |
614 |
RISC-V Cores, SoC platforms and SoCs |
Jul 15, 2022 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Sep 07, 2021 |
|
None |
3 |
RISC-V Cores, SoC platforms and SoCs |
Apr 14, 2023 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Dec 06, 2022 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Apr 19, 2022 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Mar 14, 2024 |
|
C |
854 |
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more |
Aug 31, 2022 |
|
C |
3 |
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more |
Feb 17, 2023 |
|
C |
4 |
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more |
Apr 11, 2023 |
|
C |
2 |
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more |
Apr 03, 2023 |
|
C |
3 |
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more |
Mar 30, 2023 |
|
None |
2 |
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more |
Jun 10, 2021 |
|
Python |
2 |
Fun with some DSP cores inside some phone-SoCs |
Apr 25, 2023 |
|
Verilog |
63 |
Basic RISC-V Test SoC |
Apr 22, 2023 |
|
Verilog |
2 |
M-extension for RISC-V cores. |
Oct 23, 2022 |
|
SystemVerilog |
98 |
RISC-V Debug Support for our PULP RISC-V Cores |
Jul 24, 2022 |
|
SystemVerilog |
5 |
Collection of IP cores usable to lowRISC SoC |
Mar 16, 2022 |
|
None |
67 |
CORE-V Family of RISC-V Cores |
Aug 13, 2022 |
|
None |
2 |
ISP tool & library for Bouffalo Labs RISC-V Microcontrollers and SoCs |
Dec 21, 2022 |
|
C |
75 |
ISP tool & library for Bouffalo Labs RISC-V Microcontrollers and SoCs |
May 23, 2023 |
|
None |
5 |
L2:WCH 120MHz RISC-V3A SoC (CH565) |
Nov 11, 2022 |
|
Verilog |
3 |
RISC-V SoC featuring zero-riscy core. |
Feb 21, 2022 |
|
Scala |
1040 |
RISC-V SoC designed by students in UCAS |
Aug 06, 2022 |
|
C |
2 |
Linux Kernel Source for Sophgo RISC-V SoC |
Mar 18, 2023 |
|
SystemVerilog |
803 |
A directory of Western Digital’s RISC-V SweRV Cores |
Sep 20, 2022 |
|
Rust |
4 |
Low level access to SiFive RISC-V processor cores |
Oct 14, 2022 |
|
SystemVerilog |
3 |
A directory of Western Digital’s RISC-V SweRV Cores |
Jan 29, 2022 |
|
None |
3 |
MathWorks Petalinux system for Zynq SoC platforms |
Nov 17, 2021 |
|
Rust |
2 |
Using Rust on a customized LiteX SoC (RISC-V). |
Mar 21, 2023 |
|
C |
14 |
L2 R6: WCH 120MHz RISC-V3A USB3.0 SoC (CH569) |
Feb 18, 2023 |
|
C |
9 |
L2 R2: WCH RISC-V BLE SoC (CH573/CH571) |
Mar 20, 2023 |
|
Verilog |
14 |
Dual-core RISC-V SoC with JTAG, atomics, SDRAM |
Aug 02, 2022 |
|
C |
2 |
L2 R2:WCH 144MHz RISC-V4C BLE SoC(CH32V208) |
Apr 27, 2023 |
|
None |
3 |
L4 R4:32-bit RISC-V WiFi + BT SoC |
Dec 15, 2023 |
|
Verilog |
3 |
can node from open cores, control via hps and wishbone from de0-nano-soc |
Feb 13, 2023 |
|
C |
228 |
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy |
May 05, 2023 |
|
Verilog |
9 |
RISC-V SoC designed for the Efabless Open MPW Program |
Sep 21, 2022 |
|
Python |
8 |
RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator |
Dec 31, 2021 |
|
Python |
52 |
Example litex Risc-V SOC and some example code projects in multiple languages. |
Jun 22, 2022 |
|
Makefile |
125 |
Documentation for the OpenHW Group's set of CORE-V RISC-V cores |
Aug 09, 2022 |
|
Assembly |
212 |
Functional verification project for the CORE-V family of RISC-V cores. |
Aug 17, 2022 |
|
C |
10 |
L2 R2:WCH 80MHz RISC-V4A BLE SoC (CH583/CH582/CH581) |
Mar 09, 2023 |
|
None |
3 |
L6 R5:RISC-V 400MHz Dual Core AIoT 0.2TOPS SoC (K210) |
Dec 09, 2022 |
|
None |
2 |
L7 R5:RISC-V 800MHz Dual Core AIoT (2.5TOPS) SoC (K510) |
Sep 02, 2022 |
|
None |
2 |
Hardware abstraction level (HAL) for HiSilicon Hi3861 RISC-V Radio SoC |
Oct 30, 2020 |
|
Python |
2 |
MicroPython auf SiPEED M1 Modules incl. Kendryte K210 RISC-V SoC |
Sep 17, 2021 |
|
Verilog |
50 |
A small SoC with a pipeline 32-bit RISC-V CPU. |
May 10, 2023 |
|
C |
149 |
Tiny FEL tools for allwinner SOC, support RISC-V D1 chip |
Apr 25, 2023 |
|
C |
7 |
Framework for writing directed diags for RISC-V CPU/SOC validation. |
Oct 12, 2023 |
|
None |
6 |
A 32bit RISC-V SoC on FPGA (EG4S20) that supports RT-Thread. |
Jun 01, 2022 |