|
C |
17 |
A small test SoC for various soft-CPUs (Cortex-M0, RISC-V) |
Apr 17, 2023 |
|
Verilog |
3 |
Cramium Test SoC |
Jan 15, 2023 |
|
None |
614 |
RISC-V Cores, SoC platforms and SoCs |
Jul 15, 2022 |
|
None |
5 |
L2:WCH 120MHz RISC-V3A SoC (CH565) |
Nov 11, 2022 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Sep 07, 2021 |
|
None |
3 |
RISC-V Cores, SoC platforms and SoCs |
Apr 14, 2023 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Dec 06, 2022 |
|
Verilog |
3 |
RISC-V SoC featuring zero-riscy core. |
Feb 21, 2022 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Apr 19, 2022 |
|
None |
3 |
RISC-V Cores, SoC platforms and SoCs |
Jan 07, 2023 |
|
None |
2 |
RISC-V Cores, SoC platforms and SoCs |
Mar 14, 2024 |
|
Scala |
1040 |
RISC-V SoC designed by students in UCAS |
Aug 06, 2022 |
|
C |
2 |
Linux Kernel Source for Sophgo RISC-V SoC |
Mar 18, 2023 |
|
Rust |
2 |
Using Rust on a customized LiteX SoC (RISC-V). |
Mar 21, 2023 |
|
C |
14 |
L2 R6: WCH 120MHz RISC-V3A USB3.0 SoC (CH569) |
Feb 18, 2023 |
|
C |
9 |
L2 R2: WCH RISC-V BLE SoC (CH573/CH571) |
Mar 20, 2023 |
|
Verilog |
14 |
Dual-core RISC-V SoC with JTAG, atomics, SDRAM |
Aug 02, 2022 |
|
C |
2 |
L2 R2:WCH 144MHz RISC-V4C BLE SoC(CH32V208) |
Apr 27, 2023 |
|
None |
3 |
L4 R4:32-bit RISC-V WiFi + BT SoC |
Dec 15, 2023 |
|
Verilog |
8 |
RISC-V SOC (both single and pipeline) implemented in Verilog. Passed all test codes provided by … |
Sep 24, 2022 |
|
Scala |
108 |
RISC-V Torture Test |
Aug 15, 2022 |
|
Verilog |
9 |
RISC-V SoC designed for the Efabless Open MPW Program |
Sep 21, 2022 |
|
Python |
8 |
RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator |
Dec 31, 2021 |
|
Python |
3 |
Test of LiteX standalone SoC generator. |
Jun 28, 2022 |
|
None |
3 |
RISC-V Core Test Framework |
Feb 08, 2023 |
|
C |
10 |
L2 R2:WCH 80MHz RISC-V4A BLE SoC (CH583/CH582/CH581) |
Mar 09, 2023 |
|
None |
3 |
L6 R5:RISC-V 400MHz Dual Core AIoT 0.2TOPS SoC (K210) |
Dec 09, 2022 |
|
None |
2 |
L7 R5:RISC-V 800MHz Dual Core AIoT (2.5TOPS) SoC (K510) |
Sep 02, 2022 |
|
None |
2 |
Hardware abstraction level (HAL) for HiSilicon Hi3861 RISC-V Radio SoC |
Oct 30, 2020 |
|
Python |
2 |
MicroPython auf SiPEED M1 Modules incl. Kendryte K210 RISC-V SoC |
Sep 17, 2021 |
|
Verilog |
50 |
A small SoC with a pipeline 32-bit RISC-V CPU. |
May 10, 2023 |
|
C |
149 |
Tiny FEL tools for allwinner SOC, support RISC-V D1 chip |
Apr 25, 2023 |
|
C |
7 |
Framework for writing directed diags for RISC-V CPU/SOC validation. |
Oct 12, 2023 |
|
Verilog |
41 |
Basic Peripheral SoC (SPI, GPIO, Timer, UART) |
Mar 24, 2023 |
|
C++ |
10 |
A Basic C++ RISC-V Emulator |
Oct 20, 2022 |
|
None |
6 |
A 32bit RISC-V SoC on FPGA (EG4S20) that supports RT-Thread. |
Jun 01, 2022 |
|
Verilog |
6 |
A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga) |
May 08, 2022 |
|
Verilog |
7 |
A 32-bit RISC-V SoC on FPGA that supports RT-Thread. |
Dec 27, 2021 |
|
Python |
13 |
A 32-bit RISC-V SoC on FPGA that supports RT-Thread. |
May 11, 2022 |
|
None |
2 |
L4 R3:bouffalolab WiFi6/BT/ZigBee 320MHz RISC-V SoC (BL616/ BL618) |
Mar 01, 2023 |
|
C |
4 |
L2 R2:Espressif 160MHz RISC-V Wi-Fi/BLE SoC (ESP32-C3) |
Mar 04, 2023 |
|
None |
2 |
L2 R2:Telink 96MHz RISC-V BLE/Matter SoC (TLSR9218/TLSR9215/TLSR9213) |
Apr 01, 2023 |
|
SystemVerilog |
7 |
[Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core. |
Feb 24, 2023 |
|
None |
3 |
High Quality RISC-V Test Suites |
Mar 17, 2022 |
|
Rust |
4 |
RISC-V SBI environment test suite |
Aug 30, 2022 |
|
C |
2 |
Zephyr test and demo applications targeting PolarFire SoC |
May 11, 2023 |
|
Python |
52 |
Example litex Risc-V SOC and some example code projects in multiple languages. |
Jun 22, 2022 |
|
Rust |
53 |
Hardware Abstract Layer for BL602 RISC-V WiFi + BLE SoC in embedded Rust |
Jul 24, 2022 |
|
C |
462 |
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro |
Apr 27, 2023 |
|
C |
2 |
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro |
Apr 11, 2023 |