|
Verilog |
2 |
FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and … |
May 26, 2022 |
|
None |
8 |
Feather with ICE40 FPGA |
Jun 30, 2021 |
|
Verilog |
10 |
Implementation of ECC on FPGA-Zynq7000 SoC |
Jan 25, 2022 |
|
Verilog |
3 |
SoC for Pblaze FPGA |
Apr 17, 2023 |
|
Shell |
9 |
Workflow for icestorm Lattice ice40 FPGA tools |
Dec 01, 2020 |
|
C |
7 |
STM32-based USB loader for iCE40 FPGA |
Nov 14, 2022 |
|
Scala |
106 |
SoC based on VexRiscv and ICE40 UP5K |
Oct 18, 2022 |
|
Scala |
2 |
SoC based on VexRiscv and ICE40 UP5K |
Oct 24, 2022 |
|
HTML |
12 |
Combined ESP32C3 and iCE40 FPGA board |
Jul 19, 2022 |
|
Verilog |
6 |
A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga) |
May 08, 2022 |
|
Verilog |
7 |
A 32-bit RISC-V SoC on FPGA that supports RT-Thread. |
Dec 27, 2021 |
|
Python |
13 |
A 32-bit RISC-V SoC on FPGA that supports RT-Thread. |
May 11, 2022 |
|
Verilog |
55 |
sliding DFT for FPGA, targetting Lattice ICE40 1k |
Jul 20, 2022 |
|
C |
55 |
Untethered (stand-alone) FPGA implementation of the lowRISC SoC |
Dec 25, 2021 |
|
None |
2 |
Gowin LittleBee FPGA SoC |
Feb 14, 2024 |
|
SystemVerilog |
6 |
ICE40 FPGA configuration: SSD1306 to VGA converter |
Dec 25, 2022 |
|
Verilog |
7 |
Lattice iCE40 FPGA experiments - Work in progress |
Nov 30, 2022 |
|
Verilog |
2 |
USB-C Dongle with ice40 UP5k FPGA |
Nov 10, 2022 |
|
C |
44 |
FPGA GPU design for DE1-SoC |
Jul 31, 2022 |
|
C |
6 |
Programmer for iCE40 FPGA boards using flashrom serprog protocol. |
Apr 18, 2023 |
|
C |
3 |
Programmer for iCE40 FPGA boards using flashrom serprog protocol. |
Feb 19, 2021 |
|
Verilog |
2 |
SoC FPGA interface HDL codes |
Jun 04, 2022 |
|
Verilog |
2 |
ZX81 on the Blackice Mx ice40 FPGA board |
Jul 18, 2022 |
|
Verilog |
3 |
Upduino v2 with the ice40 up5k FPGA demos |
May 26, 2022 |
|
Verilog |
50 |
FPGA dev board based on Lattice iCE40 8k |
Jul 01, 2022 |
|
Verilog |
65 |
Upduino v2 with the ice40 up5k FPGA demos |
Jul 29, 2022 |
|
C++ |
3 |
Implementation of Greedy String Art Calculation on Altera DE1-SoC FPGA |
Aug 28, 2021 |
|
Forth |
4 |
CPU and Forth system for the iCE40-HX8K FPGA board |
Mar 31, 2021 |
|
Assembly |
2 |
16 bit microprocessor for FPGA |
May 11, 2023 |
|
Assembly |
5 |
A FPGA friendly 32 bit RISC-V CPU implementation |
May 26, 2022 |
|
Assembly |
2 |
A FPGA friendly 32 bit RISC-V CPU implementation |
Jul 18, 2022 |
|
Assembly |
2 |
A FPGA friendly 32 bit RISC-V CPU implementation |
Jul 18, 2021 |
|
Assembly |
1685 |
A FPGA friendly 32 bit RISC-V CPU implementation |
Oct 19, 2022 |
|
Assembly |
2 |
A FPGA friendly 32 bit RISC-V CPU implementation |
Nov 05, 2022 |
|
Assembly |
2 |
A FPGA friendly 32 bit RISC-V CPU implementation |
Nov 22, 2022 |
|
Verilog |
164 |
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation |
Apr 07, 2023 |
|
None |
2 |
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation |
Mar 26, 2022 |
|
KiCad |
4 |
Poncho FPGA para la EDU CIAA basado en iCE40 |
Dec 07, 2020 |
|
Rust |
65 |
iCE40 FPGA, SPI flash, and CMSIS-DAP SWD programmer |
May 18, 2023 |
|
SystemVerilog |
2 |
32-bit RISC-V system on chip for iCE40 FPGAs |
Jan 20, 2021 |
|
VHDL |
2 |
8-bit CPU made for FPGA |
Oct 02, 2022 |
|
Verilog |
2 |
SOC system using verilog on FPGA devices. |
Jul 10, 2020 |
|
Verilog |
3 |
An Universal FPGA Framework for SoC Simulation and Verification |
Feb 10, 2023 |
|
Verilog |
3 |
OpenRISC SOC for the De0 Nano FPGA dev board |
Jan 29, 2022 |
|
VHDL |
5 |
FPGA-SoC-Linux example(1) binary and project and test code for DE0-Nano-SoC |
Nov 24, 2021 |
|
C |
9 |
Processor-FPGA transfer rate measurements in CycloneV-SoC |
Jul 02, 2022 |
|
C |
2 |
FPGA-SoC-Linux example(1) source code repository |
Mar 12, 2019 |
|
VHDL |
2 |
An opensource ariane based SoC on aws-fpga |
Mar 27, 2022 |
|
SystemVerilog |
5 |
32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs |
Jan 30, 2022 |
|
C |
17 |
Acorn Atom implementation for the Ice40 (myStorm BlackIce) |
May 02, 2023 |