VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

Stars

5

Forks

1

Language

Assembly

Last Updated

May 26, 2022

Similar Repos
Repo Language Stars Description Updated At
Assembly 2 A FPGA friendly 32 bit RISC-V CPU implementation Jul 18, 2022
Assembly 2 A FPGA friendly 32 bit RISC-V CPU implementation Jul 18, 2021
Assembly 1685 A FPGA friendly 32 bit RISC-V CPU implementation Oct 19, 2022
Assembly 2 A FPGA friendly 32 bit RISC-V CPU implementation Nov 05, 2022
Assembly 2 A FPGA friendly 32 bit RISC-V CPU implementation Nov 22, 2022
Verilog 567 32-bit Superscalar RISC-V CPU Apr 24, 2023
VHDL 2 8-bit CPU made for FPGA Oct 02, 2022
Verilog 3 RISC-V CPU implementation Feb 05, 2022
VHDL 7 VHDL implementation of a 16-bit RISC processor targeting the BASYS3 FPGA Apr 25, 2021
SystemVerilog 2 FPGA setup with memory and Risc V CPU May 14, 2023
SystemVerilog 5 A Single Cycle Risc-V 32 bit CPU Apr 04, 2023
VHDL 12 My 32-bit RISC CPU for smallish FPGAs Feb 01, 2023
Verilog 9 Implementing a RISC-V CPU on FPGA(Cyclone II) Apr 12, 2023
Verilog 21 A 16-bit Hack CPU from scratch on FPGA. Aug 02, 2022
Rust 5 Research towards the Implementation of a P2P-Network on an FPGA with RISC-V soft-CPU Aug 04, 2022
Python 88 Resource-efficient 16-bit CPU architecture for FPGA control plane Dec 05, 2022
Verilog 50 A small SoC with a pipeline 32-bit RISC-V CPU. May 10, 2023
Verilog 6 A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga) May 08, 2022
Verilog 7 A 32-bit RISC-V SoC on FPGA that supports RT-Thread. Dec 27, 2021
Python 13 A 32-bit RISC-V SoC on FPGA that supports RT-Thread. May 11, 2022
Assembly 15 Implementation of the 65C02 CPU suitable for FPGA. Oct 19, 2022
Verilog 2 An experimental CPU implementation for FPGA in verilog. Oct 11, 2022
SystemVerilog 5 system verilog implementation of RISC-V ISA for FPGA Sep 20, 2022
Verilog 3 Verilog implementation of the 32-bit RISC processor. May 23, 2022
CSS 13 The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture. Jan 20, 2022
SystemVerilog 7 [Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core. Feb 24, 2023
Python 2 Primitive CPU implementation in Python using RISC-V ISA Mar 02, 2024
SystemVerilog 15 A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board Apr 13, 2023
SystemVerilog 15 Cycle accurate FPGA implementation of various 6502 CPU variants Apr 07, 2022
VHDL 3 VHDL implementation of a simple MISP CPU on FPGA Nov 23, 2018
SystemVerilog 13 Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip. May 14, 2023
Verilog 8 Verilog Implementation of a 32-bit Multicycle CPU Oct 19, 2021
SystemVerilog 229 RISC-V CPU Core Apr 22, 2023
Verilog 2 32 bit RISC Processor Jun 11, 2021
Verilog 17 32-bit RISC processor May 16, 2022
C++ 2 16-Bit CPU May 03, 2023
VHDL 374 A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz May 11, 2023
Scala 8 SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype Feb 15, 2022
Verilog 2 An 8-bit SoC for implementation on an iCE40 FPGA. Apr 19, 2023
Verilog 773 RISC-V CPU Core (RV32IM) Apr 23, 2023
None 2 RISC-V CPU Core (RV32IM) Dec 12, 2021
C++ 12 RISC-V SST CPU Component Apr 19, 2023
Batchfile 3 A pipelined RISC-V CPU Sep 07, 2023
VHDL 2 Design and VHDL implementation of RISC CPU with 5 stages pipeline Jan 19, 2021
SystemVerilog 787 Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. Aug 12, 2022
None 2 Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. Aug 23, 2021
None 2 Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. May 17, 2021
None 2 Playing with FPGA and RISC-V Jan 08, 2021
VHDL 30 FPGA optimized RISC-V (RV32IM) implemenation Apr 26, 2023
Verilog 11 PolarFire FPGA sample RISC-V designs Jan 28, 2023