DRIM-S

DUTH RISC-V Superscalar Microprocessor

Stars

14

Forks

2

Language

SystemVerilog

Last Updated

May 06, 2023

Similar Repos
Repo Language Stars Description Updated At
Verilog 567 32-bit Superscalar RISC-V CPU Apr 24, 2023
Haskell 29 Superscalar RISC-V processor written in Clash. Jul 31, 2022
Python 5 A RISC-V superscalar front-end simulator. Jul 15, 2021
SystemVerilog 16 DUTH RISC-V Microprocessor Apr 13, 2023
Verilog 2 Single Cycle In-Order SuperScalar RISC-V RV32IM implementations Nov 14, 2021
Verilog 2 Single Cycle In-Order SuperScalar RISC-V RV32IM implementations Nov 14, 2021
Scala 2 A Rocket-based RISC-V superscalar in-order core Jun 01, 2023
SystemVerilog 3 Toy RISC microprocessor in Verilog for Altera FPGA Jun 20, 2021
C++ 4 DUTH RISC V Microprocessor for High Level Synthesis Mar 01, 2023
C++ 12 Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model Dec 01, 2022
VHDL 3 RISC-V based microprocessor system for Altera DE0 FPGA board May 07, 2023
Bluespec 13 RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT Apr 21, 2023
SystemVerilog 4 Moving Average Jan 28, 2022
SystemVerilog 4 Collaborative project to create an advanced GPU for the Microcom computer. Jun 12, 2022
SystemVerilog 4 SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 … May 25, 2022
SystemVerilog 4 This example .BMP generator and ASCII script file reader can be adapted to test code … May 25, 2022
SystemVerilog 4 FPGA low latency 10GBASE-R PCS May 19, 2022
SystemVerilog 4 A continually growing system verilog parts library Dec 09, 2021
SystemVerilog 4 基于FPGA的CNN图像分类系统 May 06, 2022
SystemVerilog 4 Intel CPU Garage Challenge Jun 13, 2022
SystemVerilog 4 system verilog course labs Nov 09, 2021
SystemVerilog 4 Hardware-Software codesign project. Dec 12, 2021
SystemVerilog 4 Verilog code for a simple synth module; developed on TinyFPGA BX Jul 18, 2022
    verilator-dynamic-scheduler-tests
SystemVerilog 4 None Mar 04, 2022
SystemVerilog 4 まともなRISC-V CPU Jul 18, 2022
SystemVerilog 4 Goal: Write an even higher performing solution generator Feb 22, 2021
SystemVerilog 4 Verification IP for APB protocol Jul 30, 2022
    apb_spi_master
SystemVerilog 4 None Aug 07, 2022
    axi2mem
SystemVerilog 4 None Jan 21, 2022
SystemVerilog 4 RISC-V Core Local Interrupt Controller (CLINT) Jul 14, 2022
    cluster_interconnect
SystemVerilog 4 None Feb 17, 2022
SystemVerilog 4 IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs Feb 07, 2022
SystemVerilog 4 Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores Jun 15, 2022
SystemVerilog 4 Neural Engine, 16 input channels Jul 18, 2022
    redundancy_cells
SystemVerilog 4 None Jun 29, 2022
    udma_core
SystemVerilog 4 None Mar 30, 2022
    udma_qspi
SystemVerilog 4 None Jun 05, 2022
    svlint-action
SystemVerilog 4 None Sep 17, 2020
SystemVerilog 4 A simulated memory controller for use in FPGA designs that want to model real system … Jul 12, 2021
SystemVerilog 4 Financial Technology with SoC-NTM verified with UVM/OSVVM/FV Jul 19, 2022
SystemVerilog 4 A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA) Aug 06, 2022
SystemVerilog 4 RISC-V assembler/dis-assembler written in SystemVerilog Nov 18, 2020
SystemVerilog 5 🎓 Repositório com as atividades desenvolvidas ao longo da disciplina de laboratório de organização e … Jun 01, 2022
SystemVerilog 5 8086-compatible cpu May 06, 2022
SystemVerilog 5 SPIで制御出来るアクセラレータ Nov 17, 2021
SystemVerilog 5 Verification IP for SPI protocol Jul 30, 2022
SystemVerilog 5 A chisel3 wrapper for pulp-platform/fpnew Aug 01, 2020
SystemVerilog 5 APB Logic Jun 14, 2022
SystemVerilog 5 IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system May 10, 2022
SystemVerilog 5 Development Fork (unstable) Apr 19, 2022