|
VHDL |
3 |
AXI Interface Converter (Stream, Memory-Mapped and Lite) |
Dec 12, 2023 |
|
C |
40 |
AMBA bus generator including AXI, AHB, and APB |
Aug 17, 2022 |
|
C |
3 |
Helper library for memory mapped bus access |
Jun 28, 2021 |
|
VHDL |
13 |
AXI memory-mapped VGA module originally designed for the Avent Zedboard |
Feb 20, 2023 |
|
VHDL |
6 |
Sample HDL Code that Interfaces to the Zynq AXI Bus |
Mar 23, 2023 |
|
Tcl |
2 |
Example design for FPGA Drive using the AXI Memory Mapped to PCI Express Bridge IP |
Dec 12, 2017 |
|
Python |
2 |
A faster & low-memory replacement for geoip-lite, a node library that maps IPs to geographical … |
Oct 20, 2023 |
|
Rust |
2 |
A faster & low-memory replacement for geoip-lite, a node library that maps IPs to geographical … |
Jul 21, 2023 |
|
Verilog |
8 |
5 stage pipelined RISC-V core with AXI3 bus protocol between the directly mapped cache and … |
May 17, 2023 |
|
SystemVerilog |
4 |
Moving Average |
Jan 28, 2022 |
|
SystemVerilog |
4 |
Collaborative project to create an advanced GPU for the Microcom computer. |
Jun 12, 2022 |
|
SystemVerilog |
4 |
SystemVerilog HDMI encoder, serializer & PLL generator. Tested on Cyclone IV-E, Compatible with Quartus 13.0 … |
May 25, 2022 |
|
SystemVerilog |
4 |
This example .BMP generator and ASCII script file reader can be adapted to test code … |
May 25, 2022 |
|
SystemVerilog |
4 |
FPGA low latency 10GBASE-R PCS |
May 19, 2022 |
|
SystemVerilog |
4 |
A continually growing system verilog parts library |
Dec 09, 2021 |
|
SystemVerilog |
4 |
基于FPGA的CNN图像分类系统 |
May 06, 2022 |
|
SystemVerilog |
4 |
Intel CPU Garage Challenge |
Jun 13, 2022 |
|
SystemVerilog |
4 |
system verilog course labs |
Nov 09, 2021 |
|
SystemVerilog |
4 |
Hardware-Software codesign project. |
Dec 12, 2021 |
|
SystemVerilog |
4 |
Verilog code for a simple synth module; developed on TinyFPGA BX |
Jul 18, 2022 |
verilator-dynamic-scheduler-tests
|
SystemVerilog |
4 |
None |
Mar 04, 2022 |
|
SystemVerilog |
4 |
まともなRISC-V CPU |
Jul 18, 2022 |
|
SystemVerilog |
4 |
Goal: Write an even higher performing solution generator |
Feb 22, 2021 |
|
SystemVerilog |
4 |
Verification IP for APB protocol |
Jul 30, 2022 |
|
SystemVerilog |
4 |
None |
Aug 07, 2022 |
|
SystemVerilog |
4 |
None |
Jan 21, 2022 |
|
SystemVerilog |
4 |
RISC-V Core Local Interrupt Controller (CLINT) |
Jul 14, 2022 |
|
SystemVerilog |
4 |
None |
Feb 17, 2022 |
|
SystemVerilog |
4 |
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs |
Feb 07, 2022 |
|
SystemVerilog |
4 |
Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores |
Jun 15, 2022 |
|
SystemVerilog |
4 |
Neural Engine, 16 input channels |
Jul 18, 2022 |
|
SystemVerilog |
4 |
None |
Jun 29, 2022 |
|
SystemVerilog |
4 |
None |
Mar 30, 2022 |
|
SystemVerilog |
4 |
None |
Jun 05, 2022 |
|
SystemVerilog |
4 |
None |
Sep 17, 2020 |
|
SystemVerilog |
4 |
A simulated memory controller for use in FPGA designs that want to model real system … |
Jul 12, 2021 |
|
SystemVerilog |
4 |
Financial Technology with SoC-NTM verified with UVM/OSVVM/FV |
Jul 19, 2022 |
|
SystemVerilog |
4 |
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA) |
Aug 06, 2022 |
|
SystemVerilog |
4 |
RISC-V assembler/dis-assembler written in SystemVerilog |
Nov 18, 2020 |
|
SystemVerilog |
5 |
🎓 Repositório com as atividades desenvolvidas ao longo da disciplina de laboratório de organização e … |
Jun 01, 2022 |
|
SystemVerilog |
5 |
8086-compatible cpu |
May 06, 2022 |
|
SystemVerilog |
5 |
SPIで制御出来るアクセラレータ |
Nov 17, 2021 |
|
SystemVerilog |
5 |
Verification IP for SPI protocol |
Jul 30, 2022 |
|
SystemVerilog |
5 |
A chisel3 wrapper for pulp-platform/fpnew |
Aug 01, 2020 |
|
SystemVerilog |
5 |
APB Logic |
Jun 14, 2022 |
|
SystemVerilog |
5 |
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system |
May 10, 2022 |
|
SystemVerilog |
5 |
Development Fork (unstable) |
Apr 19, 2022 |
|
SystemVerilog |
5 |
Collection of IP cores usable to lowRISC SoC |
Mar 16, 2022 |
|
SystemVerilog |
5 |
Direct Access Memory for MPSoC |
Aug 12, 2022 |
|
SystemVerilog |
5 |
Hardware Description Language Translator |
Feb 19, 2022 |