|
MATLAB |
2 |
Final project for EE326 Digital Image Processing @ SUSTech |
Apr 23, 2023 |
|
Verilog |
2 |
Flappy Bird running on FPGA. Project for SUSTech CS211 Digital Logic(H). |
Nov 23, 2023 |
|
Verilog |
2 |
Final project of Fall 2017 Digital Logic at Tongji Univ. |
Mar 22, 2021 |
|
None |
5 |
🚗 A Car Parking Simulator made in LogicWorks 5 as a final project for the … |
Jul 13, 2022 |
|
Verilog |
4 |
SUSTech CS207 Digital Design 2018Fall Materials. |
Jun 26, 2022 |
|
Python |
4 |
Data Link Layer Emulator for SUSTech Computer Network Course Final Project |
Dec 11, 2017 |
|
Python |
10 |
This is the project repo for the final project of the Udacity Self-Driving Car Nanodegree: … |
Jan 24, 2022 |
|
VHDL |
19 |
A pseudo Minecraft game running on Artix-7 FPGA in VHDL. Also the final project for … |
May 22, 2023 |
|
C# |
2 |
Final project on Digital Game Design |
Jul 02, 2022 |
|
VHDL |
3 |
🔌 Digital Logic Design project, PoliMi 2019 |
Sep 19, 2021 |
|
Jupyter Notebook |
2 |
SUSTech Course EE326, Digital Image Processing, Spring 2021 |
Apr 12, 2023 |
|
Python |
21 |
Final Year Masters Project: modal logic solver tableaux |
May 26, 2022 |
|
Kotlin |
2 |
Final project for Google Digital Garage Course |
Oct 31, 2022 |
|
Python |
2 |
2110431 Introduction to Digital Imaging Final Project |
Dec 08, 2023 |
|
LabVIEW |
2 |
LabVIEW project for Digital Logic Design course (EEC242) |
Jan 14, 2023 |
|
HTML |
2 |
Fundamental of digital logic and processor course project |
Jul 03, 2022 |
|
Jupyter Notebook |
3 |
2022 Fall Group Project@SUSTech |
Mar 29, 2023 |
|
TeX |
4 |
Course project in SUSTech CS303 |
Nov 10, 2022 |
|
Python |
3 |
Final project for 2021 PKUSZ@Digital Image Processing |
May 17, 2022 |
|
TeX |
8 |
Digital Signal Processing LABs for SUSTECH 2020 FALL (EE323).:carrot: |
Mar 15, 2023 |
|
Java |
4 |
CSE315-Digital Logic Design |
Jan 28, 2023 |
|
Verilog |
6 |
Microprocessor implemented with Verilog, for Logic Design Lab Final Project. |
May 26, 2022 |
|
Jupyter Notebook |
2 |
ECE385 (Digital Systems Laboratory) Final Project @ UIUC; On FPGA |
Dec 19, 2021 |
|
TeX |
6 |
Digital images used as illustrations in the Open Logic Project |
Feb 01, 2023 |
|
CMake |
2 |
Final System Integration Project for the Udacity Self Driving Car Nanodegree |
Jan 29, 2024 |
|
JavaScript |
7 |
CS309 Project - SUSTech User Script Tools Center |
Oct 03, 2019 |
|
Java |
11 |
Digital logic designer and simulator |
May 29, 2022 |
|
Python |
2 |
A digital logic simplification program. |
Oct 21, 2021 |
|
Rust |
2 |
Digital logic simulation in Rust |
Apr 13, 2022 |
|
None |
2 |
Digital logic reverse engineering tool |
Jun 14, 2023 |
|
Java |
2 |
Digital logic designer and simulator |
Dec 21, 2023 |
|
Go |
12 |
Golang Clean Web API (Dockerize) with a real project (Car Sale project) |
Apr 29, 2023 |
|
Verilog |
3 |
Course Project for ECN-104: Digital Logic Design at IIT Roorkee |
Nov 17, 2021 |
|
Java |
2607 |
Digital logic design tool and simulator |
Sep 02, 2022 |
|
C# |
2 |
Asynchronous event-driven digital logic simulator |
Jun 07, 2022 |
|
Verilog |
2 |
Course Work Backup for Digital Logic |
Aug 03, 2020 |
|
None |
3 |
Digital Logic Sim - Community Circuits Repository |
Apr 08, 2023 |
|
Verilog |
8 |
Digital logic necessary to debounce buttons |
Nov 22, 2022 |
|
SystemVerilog |
6 |
A collection of digital logic circuits |
Apr 30, 2023 |
|
C |
46 |
A logic analyser (digital waveform viewer) |
May 16, 2023 |
|
None |
5 |
Final project for the Digital Signal Processing course. Topic: speaker identification. |
Jun 16, 2022 |
|
SCSS |
4 |
Digiathon 2022 - TR Presidency Digital Transformation Office Digiathon Competition Final Project |
Feb 26, 2023 |
|
Matlab |
6 |
Final project of digital image processing (Breast cancer classification) using Matlab |
Oct 19, 2022 |
|
C# |
5 |
Car Project |
Feb 12, 2023 |
|
VHDL |
3 |
TSEA43 |
Mar 16, 2017 |
|
VHDL |
4 |
None |
Jul 15, 2020 |
|
VHDL |
4 |
Design and implementation of a pipelined Bfloat16 Floating Point Arithmetic Unit using VHDL. This unit … |
Apr 18, 2022 |
|
VHDL |
4 |
None |
Apr 11, 2022 |
|
VHDL |
4 |
bnn accelerator |
Jan 12, 2022 |
|
VHDL |
4 |
基于MIPS指令集的cpu设计,能够通过龙芯杯个人赛测试。 |
Jul 02, 2022 |