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Verilog |
3 |
CS207 Fall 2018 Digital Clock |
Oct 02, 2020 |
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CSS |
10 |
Materials for guest lecture on dask for Harvard CS207 |
Oct 17, 2022 |
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None |
6 |
SUSTech CS201 Discrete Mathematics Materials in 2019Spring |
Jun 26, 2022 |
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HTML |
2 |
CS207-Project |
Jan 28, 2023 |
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MATLAB |
2 |
Final project for EE326 Digital Image Processing @ SUSTech |
Apr 23, 2023 |
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Jupyter Notebook |
2 |
SUSTech Course EE326, Digital Image Processing, Spring 2021 |
Apr 12, 2023 |
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Jupyter Notebook |
15 |
Course materials of SUSTech CS308 Computer Vision (2021 fall) |
Mar 11, 2022 |
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VHDL |
2 |
Digital Logic Final Project of SUSTech: A Real Car |
Mar 28, 2023 |
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HTML |
2 |
OOP Project - CS207 Course |
Dec 30, 2021 |
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TeX |
8 |
Digital Signal Processing LABs for SUSTECH 2020 FALL (EE323).:carrot: |
Mar 15, 2023 |
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Processing |
4 |
digital design |
Sep 18, 2022 |
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Verilog |
2 |
Flappy Bird running on FPGA. Project for SUSTech CS211 Digital Logic(H). |
Nov 23, 2023 |
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None |
2 |
PCB design materials |
Aug 15, 2017 |
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Rich Text Format |
6 |
ONS Digital design |
Feb 13, 2022 |
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Tcl |
19 |
Digital System Design |
Nov 16, 2022 |
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VHDL |
28 |
Digital design circuits |
May 02, 2023 |
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Verilog |
2 |
Digital circuit course design Digital clock |
Aug 03, 2022 |
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C++ |
9 |
SUSTech CS205 (C/C++ Program Design) Projects, taught by Shiqi Yu, 2022F |
May 07, 2023 |
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Jupyter Notebook |
2 |
Phenome 2020 Digital Phenotyping workshop materials |
May 25, 2021 |
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JavaScript |
3 |
WeChat Mini app for https://github.com/SUSTech-CRA/sustech-online-ng |
Sep 15, 2023 |
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Java |
4 |
CSE315-Digital Logic Design |
Jan 28, 2023 |
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CSS |
2 |
Digital Design Project 2017 |
May 28, 2019 |
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None |
17 |
Defra Digital Design resources |
Jun 29, 2022 |
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TypeScript |
30 |
Neumorphism design digital clock |
Jun 22, 2022 |
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Verilog |
14 |
Digital Design Express Course |
Feb 13, 2023 |
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Verilog |
3 |
Digital Design Introduction Labs |
May 16, 2021 |
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TeX |
572 |
Digital Design with Chisel |
May 12, 2023 |
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MATLAB |
3 |
Digital Filter Design Samples |
Jan 18, 2023 |
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Jupyter Notebook |
2 |
Digital Design Colab Examples |
Oct 25, 2023 |
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CSS |
2 |
digital agency website design |
Mar 25, 2023 |
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C |
2 |
OS course of SUSTech |
Oct 30, 2019 |
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None |
7 |
Design materials for Dark Reader |
Jul 19, 2022 |
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Python |
3 |
ML System Design lectures materials |
Jun 05, 2023 |
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Jupyter Notebook |
17 |
Digital Signals Theory book and source materials |
Nov 27, 2022 |
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None |
2 |
Opensource, Skywater PDK, Digital design, OPENLANE, Analog design |
May 02, 2022 |
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SCSS |
5 |
Design System for Digital Publishing |
Apr 13, 2022 |
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JavaScript |
5 |
Statistics Norway's digital design system |
Mar 08, 2022 |
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Verilog |
2 |
EE342 (Digital System Design) Labworks |
Apr 04, 2022 |
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Verilog |
2 |
HDL in Digital System Design |
Jan 14, 2023 |
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None |
3 |
DTC Digital Design Project Template |
Dec 22, 2022 |
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Verilog |
14 |
Documentation for Digital Design course |
May 05, 2023 |
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Verilog |
3 |
SJTU CS145 Computer Architecture Labs. |
Apr 08, 2022 |
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Verilog |
4 |
This is the design experiment of a third-year computer composition principle course in a university. … |
Mar 15, 2021 |
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Verilog |
4 |
Skywater 130nm LDO parts and DPLL |
May 03, 2022 |
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Verilog |
4 |
None |
Apr 11, 2022 |
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Verilog |
4 |
[DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs |
Mar 27, 2022 |
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Verilog |
4 |
UVM Testbench for Keccak sha3 core downloaded from Opencores https://opencores.org/projects/sha3 |
Mar 30, 2022 |
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Verilog |
4 |
None |
Jun 02, 2022 |
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Verilog |
4 |
Comprehensive hardware library in Verilog for hardware primitives |
Oct 30, 2021 |
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Verilog |
4 |
Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor … |
May 25, 2022 |