|
Scala |
8 |
SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype |
Feb 15, 2022 |
|
Verilog |
3 |
This repository contains the design files of RISC-V Single Cycle Core |
Apr 28, 2023 |
|
Verilog |
3 |
Open source RISC-V IP core for FPGA/ASIC design |
Aug 09, 2022 |
|
None |
3 |
This Repository contains the Logisim design files of RISC-V Single Cycle Core |
Apr 28, 2023 |
|
Verilog |
3 |
The Ultra-Low Power RISC Core |
Apr 28, 2020 |
|
None |
34 |
The Ultra-Low Power RISC Core |
Feb 20, 2023 |
|
Haskell |
3 |
Extensible implementation of the RISC-V ISA based on FreeMonads |
Jul 10, 2023 |
|
JetBrains MPS |
209 |
The mbeddr core. An extensible C |
Oct 15, 2022 |
|
SystemVerilog |
229 |
RISC-V CPU Core |
Apr 22, 2023 |
|
Verilog |
783 |
The Ultra-Low Power RISC-V Core |
May 04, 2023 |
|
None |
3 |
RISC-V Core Test Framework |
Feb 08, 2023 |
|
Verilog |
773 |
RISC-V CPU Core (RV32IM) |
Apr 23, 2023 |
|
None |
2 |
RISC-V CPU Core (RV32IM) |
Dec 12, 2021 |
|
Haskell |
2 |
Functionally described RISC-V core |
Jan 04, 2020 |
|
None |
14 |
Personal Proteus Design Suite libraries (schematic symbols and packages/footprints) |
May 22, 2023 |
|
None |
2 |
Various Proteus PCB Design Files (Schematic, PCB and 3D views) |
Mar 21, 2023 |
|
Python |
14 |
The sources of the online SpinalHDL doc |
Oct 04, 2022 |
|
C |
2 |
Yet another RISC-V CPU core |
Aug 16, 2020 |
|
None |
3 |
Files and docs for the Proteus |
May 17, 2023 |
|
C# |
2 |
The internal creature class for proteus. |
Mar 12, 2014 |
|
Verilog |
10 |
IOb_SoC version of the Picorv32 RISC-V Verilog IP core |
Mar 08, 2023 |
|
SystemVerilog |
4 |
RISC-V Core Local Interrupt Controller (CLINT) |
Jul 14, 2022 |
|
Tcl |
7 |
RISC-V soft-core PEs for TaPaSCo |
Jun 23, 2022 |
|
SystemVerilog |
2 |
RISC-V RV32I CPU core in SystemVerilog |
Mar 14, 2023 |
|
None |
67 |
CORE-V Family of RISC-V Cores |
Aug 13, 2022 |
|
SystemVerilog |
106 |
A simple RISC V core for teaching |
Mar 16, 2023 |
|
SystemVerilog |
6 |
RISC-V Z0 - A RISCV32-IMC CORE |
Nov 30, 2022 |
|
Verilog |
3 |
RISC-V SoC featuring zero-riscy core. |
Feb 21, 2022 |
|
Verilog |
81 |
Verilog implementation of a RISC-V core |
Apr 27, 2023 |
|
C++ |
32 |
Arduino Core for CH32V003 RISC-V microcontroller |
May 31, 2023 |
|
Python |
3 |
UCB-CS61C project3 : RISC-V CPU design |
Mar 19, 2023 |
|
None |
5 |
RISC-V formal verification on Chisel design |
Sep 29, 2022 |
|
JavaScript |
4 |
Core extensible collection of useful SCSS modules |
Sep 25, 2018 |
|
HTML |
11 |
RISC-V Ibex core with Wishbone B4 interface |
Dec 27, 2022 |
|
Verilog |
2 |
A small, light weight, RISC CPU soft core |
Jan 27, 2023 |
|
Verilog |
1028 |
A small, light weight, RISC CPU soft core |
May 05, 2023 |
|
Verilog |
2 |
RISC-V RV32E core designed for minimal area |
Sep 09, 2023 |
|
SystemVerilog |
2 |
Wolv Z1 is a RISC-V CPU core |
May 01, 2023 |
|
Julia |
777 |
Extensible, Efficient Quantum Algorithm Design for Humans. |
Apr 29, 2023 |
|
Python |
3 |
The hardware implementation of Poseidon hash function in SpinalHDL |
May 12, 2022 |
|
SystemVerilog |
54 |
4 stage, in-order, secure RISC-V core based on the CV32E40P |
Aug 11, 2022 |
|
SystemVerilog |
104 |
4 stage, in-order, compute RISC-V core based on the CV32E40P |
Jul 23, 2022 |
|
Makefile |
125 |
Documentation for the OpenHW Group's set of CORE-V RISC-V cores |
Aug 09, 2022 |
|
Assembly |
212 |
Functional verification project for the CORE-V family of RISC-V cores. |
Aug 17, 2022 |
|
Dart |
2 |
Core Library of the Legen Design Ecosystem |
Dec 14, 2022 |
|
C# |
4 |
The Repository Design Pattern in .Net Core |
May 27, 2023 |
|
Scala |
3 |
Minimal RISC-V Chisel design strictly reflecting the ISA document for verification. |
Oct 27, 2023 |
|
JavaScript |
57 |
An extensible Node.js 3D core for desktop applications |
Dec 04, 2022 |
|
SystemVerilog |
8 |
Open-Source Posit RISC-V Core with Quire Capability |
May 19, 2022 |
|
Verilog |
14 |
Dual-core RISC-V SoC with JTAG, atomics, SDRAM |
Aug 02, 2022 |