|
VHDL |
2 |
Opsis SoC based on LiteX |
May 05, 2022 |
|
Python |
2 |
Complete SoC based on litex/vexriscv |
Sep 07, 2018 |
|
Python |
2 |
Digilent's Arty SoC based on LiteX |
Nov 17, 2021 |
|
Python |
3 |
Test of LiteX standalone SoC generator. |
Jun 28, 2022 |
|
Python |
2 |
Support files for SoC devices on litex |
May 23, 2022 |
|
Rust |
2 |
Using Rust on a customized LiteX SoC (RISC-V). |
Mar 21, 2023 |
|
Python |
2 |
LiteX alternative SoC/Gateware for the LimeSDR Mini 2.0 |
May 09, 2023 |
|
Python |
6 |
Test of a RP2040 PMOD attached to a LiteX SoC. |
Oct 20, 2022 |
|
Python |
52 |
Example litex Risc-V SOC and some example code projects in multiple languages. |
Jun 22, 2022 |
|
Shell |
2 |
I2S demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board |
Jul 21, 2022 |
|
Python |
10 |
LiteX based FPGA gateware for Thunderscope. |
Aug 11, 2022 |
|
C |
5 |
FPGA code for NeTV2 |
May 08, 2021 |
|
C |
5 |
FPGA code for NeTV2 |
Feb 05, 2023 |
|
RobotFramework |
52 |
TF Lite demo on LiteX/VexRiscv soft RISC-V SoC on a Digilent Arty board |
Jul 05, 2022 |
|
VHDL |
18 |
Vivado design for basic NeTV2 FPGA with chroma-based overlay |
Jun 10, 2022 |
|
C |
3 |
Km management utility for NeTV2 |
May 03, 2020 |
|
Tcl |
4 |
EDID Snooper for NeTV2 implementation |
Jan 29, 2022 |
|
Python |
8 |
LiteX-based PCIe MITM, sniffing, fuzzing, device emulation |
Jul 21, 2022 |
|
C |
18 |
XTRX LiteX/LitePCIe based design for Julia Computing |
Jul 12, 2022 |
|
Verilog |
6 |
Chroma key IP block for NeTV2 |
Jan 29, 2022 |
|
Tcl |
7 |
HDMI/DVI decoder for NeTV2 FPGA |
Jan 29, 2022 |
|
Verilog |
5 |
DVI encoder block for NeTV2 FPGA |
Jan 29, 2022 |
|
C |
5 |
PCI memory access tools for NeTV2 |
May 03, 2020 |
|
Python |
2 |
LiteX boards files |
Nov 28, 2022 |
|
Python |
269 |
LiteX boards files |
May 03, 2023 |
|
Python |
2 |
LiteX JTAG extensions |
Sep 13, 2022 |
|
Python |
2 |
LiteX boards files |
Jun 16, 2023 |
|
Verilog |
13 |
SoC Based on ARM Cortex-M3 |
Aug 21, 2022 |
|
Verilog |
174 |
FuseSoC-based SoC for SweRV EH1 |
Aug 01, 2022 |
|
Verilog |
13 |
HDCP cipher engine for the NeTV2 FPGA |
May 09, 2023 |
|
Python |
4 |
Next Generation LiteX BuildEnv |
May 23, 2021 |
|
Python |
12 |
Simplified environment for litex |
May 23, 2022 |
|
C++ |
2 |
Litex-FPGA Linux Chainloader |
Apr 13, 2020 |
|
Python |
441 |
Linux on LiteX-VexRiscv |
Apr 28, 2023 |
|
Python |
4 |
LiteX Build Environment tool. |
Aug 23, 2022 |
|
Python |
2 |
Litex/Migen project repository |
Dec 15, 2022 |
|
Scala |
106 |
SoC based on VexRiscv and ICE40 UP5K |
Oct 18, 2022 |
|
Scala |
2 |
SoC based on VexRiscv and ICE40 UP5K |
Oct 24, 2022 |
|
TeX |
6 |
The Papers of Litex Network |
May 08, 2021 |
|
Python |
10 |
LiteX LUNA USB stack integration |
Aug 02, 2022 |
|
Python |
3 |
NaxRiscv integration test with LiteX |
Jun 17, 2022 |
|
VHDL |
6 |
NEORV32 integration test with LiteX |
Jun 30, 2022 |
|
Python |
6 |
Minimal DRAM controllers for LiteX |
Jan 10, 2023 |
|
Python |
23 |
basic example of litex on colorLight 5A-75B based on fpga_101/lab004 |
Oct 05, 2022 |
|
None |
28 |
System on Module based on StarFive 71x0 SoC. |
Jul 07, 2022 |
|
C |
17 |
A lua based firmware for wifi-soc esp8266 |
Apr 16, 2020 |
|
Verilog |
13 |
AHB-Lite based SoC for IBEX/SWERV/VEXRISC/... |
Apr 04, 2023 |
|
Verilog |
25 |
Small SERV-based SoC primarily for OpenMPW tapeout |
Feb 08, 2023 |
|
VHDL |
2 |
An opensource ariane based SoC on aws-fpga |
Mar 27, 2022 |
|
None |
3 |
SOC |
Jan 31, 2023 |