|
Common Lisp |
2 |
Global convergence of a digital Phase-Locked Loop. |
Jan 11, 2023 |
|
Verilog |
6 |
A digital phase-locked loop implemented on Spartan-6 |
Feb 28, 2022 |
|
Python |
3 |
Phase Locked Loop Neural Network |
Aug 01, 2022 |
|
C |
2 |
Phase locked loop algorithm implemented for grid synchronization. |
Jul 21, 2022 |
|
None |
7 |
VSD workshop - Phase Locked Loop(PLL) IC Design |
Mar 01, 2022 |
|
Python |
22 |
Digital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya |
Mar 08, 2022 |
|
Verilog |
65 |
A collection of phase locked loop (PLL) related projects |
Sep 30, 2022 |
|
Verilog |
7 |
Delta-Sigma modulator (DSM) for fractional phase locked loop. |
Jun 01, 2022 |
|
None |
2 |
This repository displays a detailed construct of a Digital Phase Locked Loop made in Cadence … |
Sep 08, 2022 |
|
Matlab |
3 |
Phase Locked Loop for an I-Q modulated signal with a fixed phase offset. |
Aug 01, 2022 |
|
VHDL |
3 |
More advanced phase-locked-loop project for an FPGA design course |
Nov 26, 2021 |
|
MATLAB |
2 |
MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/ |
May 20, 2022 |
|
Verilog |
7 |
A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop |
Sep 28, 2022 |
|
Python |
8 |
A Phase Vocoder implementation in Python. Phase updates are done as proposed in Miller Puckette's … |
Mar 16, 2020 |
|
SystemVerilog |
6 |
A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design … |
Aug 30, 2022 |
|
None |
7 |
All locked problems |
Apr 25, 2022 |
|
C++ |
6 |
Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop |
Nov 14, 2023 |
|
None |
13 |
KiCad project files and arduino code for an in-expensive and simple phase-locked-loop driver for piezo-electric … |
Sep 14, 2021 |
|
None |
8 |
digital tape loop / softcut m4l wrapper |
Jun 29, 2021 |
|
VHDL |
2 |
All-Digital Phase-Locked Loops (ADPLL) code in High Speed Integrated Circuit Hardware Description Language (VHDL) for … |
Jun 07, 2022 |
|
JavaScript |
4 |
VIETTEL DIGITAL TALENT 2021 - Phase 1: Training |
Jul 29, 2022 |
|
C++ |
25 |
Generic library for any voltage and current sensors. Interrupt based, implements a zero cross detector … |
Sep 17, 2022 |
|
Python |
258 |
Implementation of the PEP 3156 event-loop (asyncio) api using the Qt Event-Loop |
Nov 09, 2022 |
|
C |
2 |
Rust-locked localtime - a sound localtime implementation |
Feb 14, 2022 |
|
VHDL |
3 |
TSEA43 |
Mar 16, 2017 |
|
VHDL |
4 |
None |
Jul 15, 2020 |
|
VHDL |
4 |
Design and implementation of a pipelined Bfloat16 Floating Point Arithmetic Unit using VHDL. This unit … |
Apr 18, 2022 |
|
VHDL |
4 |
None |
Apr 11, 2022 |
|
VHDL |
4 |
bnn accelerator |
Jan 12, 2022 |
|
VHDL |
4 |
基于MIPS指令集的cpu设计,能够通过龙芯杯个人赛测试。 |
Jul 02, 2022 |
|
VHDL |
4 |
None |
Jul 17, 2022 |
|
VHDL |
4 |
A smart speaker prototype for module 11 of Electrical Engineering at University of Twente |
Mar 04, 2021 |
|
VHDL |
4 |
A VHDL implementation of VirtualWire/RadioHead |
Mar 04, 2021 |
|
VHDL |
4 |
CameraLink Gateway |
Apr 28, 2022 |
|
VHDL |
4 |
An 8-bit processor in VHDL based on a simple instruction set |
Jun 26, 2022 |
|
VHDL |
4 |
My HDL activities appear here. This is for my personal use. PPT's copyrights to University … |
Jul 20, 2022 |
|
VHDL |
4 |
My activities appear here,Copyrights to Colorado Boulder University-This is for personal use. |
Jun 03, 2022 |
|
VHDL |
4 |
A simple sprite example written in VHDL for DE10 Nano |
Mar 15, 2022 |
|
VHDL |
4 |
A simple tilemap example written in VHDL for DE10 Nano |
Mar 15, 2022 |
|
VHDL |
4 |
None |
Mar 18, 2022 |
|
VHDL |
4 |
None |
Jun 10, 2022 |
|
VHDL |
4 |
socz80 port for Altera FPGA boards |
Dec 04, 2018 |
|
VHDL |
4 |
None |
Apr 19, 2022 |
|
VHDL |
4 |
None |
Feb 14, 2021 |
|
VHDL |
4 |
Asteroids Deluxe |
Mar 11, 2022 |
|
VHDL |
4 |
Arcade games on Bally Astrocade Hardware |
Jan 19, 2022 |
|
VHDL |
4 |
Arcade: Crazy Kong for MiSTer |
Jun 10, 2021 |
|
VHDL |
4 |
Donkey Kong Junior |
Sep 22, 2021 |
|
VHDL |
4 |
Arcade: Pooyan for MiSTer |
Sep 29, 2021 |
|
VHDL |
4 |
FPGA implementation of Super Breakout arcade game released by Atari in 1978 |
May 20, 2022 |