DPLL-FPGA

A digital phase-locked loop implemented on Spartan-6

Stars

6

Forks

0

Language

Verilog

Last Updated

Feb 28, 2022

Similar Repos
Repo Language Stars Description Updated At
Common Lisp 2 Global convergence of a digital Phase-Locked Loop. Jan 11, 2023
C 2 Phase locked loop algorithm implemented for grid synchronization. Jul 21, 2022
VHDL 2 An all digital implementation of the Phase Locked Loop Oct 04, 2022
Python 3 Phase Locked Loop Neural Network Aug 01, 2022
None 7 VSD workshop - Phase Locked Loop(PLL) IC Design Mar 01, 2022
Python 22 Digital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya Mar 08, 2022
Verilog 65 A collection of phase locked loop (PLL) related projects Sep 30, 2022
Verilog 7 Delta-Sigma modulator (DSM) for fractional phase locked loop. Jun 01, 2022
None 2 This repository displays a detailed construct of a Digital Phase Locked Loop made in Cadence … Sep 08, 2022
Matlab 3 Phase Locked Loop for an I-Q modulated signal with a fixed phase offset. Aug 01, 2022
VHDL 3 More advanced phase-locked-loop project for an FPGA design course Nov 26, 2021
MATLAB 2 MathWorks-Excellence-in-Innovation/projects/Behavioral Modelling of Phase-Locked Loop using Deep Learning Techniques/ May 20, 2022
Verilog 7 A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop Sep 28, 2022
C++ 6 Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop Nov 14, 2023
SystemVerilog 6 A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design … Aug 30, 2022
None 13 KiCad project files and arduino code for an in-expensive and simple phase-locked-loop driver for piezo-electric … Sep 14, 2021
Rust 2 Phase vocoder implemented in rust. Apr 26, 2021
Python 8 A Phase Vocoder implementation in Python. Phase updates are done as proposed in Miller Puckette's … Mar 16, 2020
Verilog 4 Xilinx Spartan 3E & VHDL - Phase rangefiner / Abstract distance measurement with FFT on … May 01, 2023
None 8 digital tape loop / softcut m4l wrapper Jun 29, 2021
Python 19 Phase space generation implemented in TensorFlow Sep 17, 2022
JavaScript 4 VIETTEL DIGITAL TALENT 2021 - Phase 1: Training Jul 29, 2022
Python 2 Two phase commit and Three phase commit demo implemented by http server Dec 09, 2021
C++ 25 Generic library for any voltage and current sensors. Interrupt based, implements a zero cross detector … Sep 17, 2022
Verilog 35 A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs May 08, 2022
Scala 3 The Chisel Convert Phase implemented with JVM Panama Jan 15, 2023
C 2 A four-phase compiler implemented for css 448. Oct 15, 2013
OCaml 235 Spartan type theory Apr 21, 2023
Rust 7 Spartan on Arkworks Mar 16, 2023
Python 3 spartan:// protocol specification Apr 16, 2023
C 29 A 3 phase motor controller implemented on an STM32 Aug 29, 2022
MATLAB 7 Digital Communication Project implemented in MATLAB Jul 12, 2022
HTML 8 Our spartan simple homepage. Dec 02, 2021
JavaScript 7 DApp for Spartan Swap Jan 21, 2022
Python 25 Spartan implementation of H.O.T.T. Aug 05, 2022
Verilog 3 SJTU CS145 Computer Architecture Labs. Apr 08, 2022
Verilog 4 This is the design experiment of a third-year computer composition principle course in a university. … Mar 15, 2021
Verilog 4 Skywater 130nm LDO parts and DPLL May 03, 2022
    CREME_DIGITAL
Verilog 4 None Apr 11, 2022
Verilog 4 [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs Mar 27, 2022
Verilog 4 UVM Testbench for Keccak sha3 core downloaded from Opencores https://opencores.org/projects/sha3 Mar 30, 2022
    axi4lite_sha3
Verilog 4 None Jun 02, 2022
Verilog 4 Comprehensive hardware library in Verilog for hardware primitives Oct 30, 2021
Verilog 4 Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor … May 25, 2022
    RealCPU
Verilog 4 None Jun 07, 2022
    cpu
Verilog 4 None Jan 04, 2022
Verilog 4 FIFO implementation with different clock domains for read and write. Jun 16, 2022
Verilog 4 鉴于网上RISC v版单周期CPU完整资料较少，基本无能够直接运行版本，上传代码，仅供大家参考。相关问题可以联系作者[email protected]。 Jul 05, 2022
    caravel-LoesterSoC
Verilog 4 None Apr 14, 2022
Verilog 4 Import of the demon core from SVN http://gadgetforge.gadgetfactory.net/svn/butterflylogic/trunk/Verilog_Core/ Jul 19, 2016