R32V2020

My 32-bit RISC CPU for smallish FPGAs

Stars

12

Forks

3

Language

VHDL

Last Updated

Feb 01, 2023

Similar Repos
Repo Language Stars Description Updated At
Verilog 567 32-bit Superscalar RISC-V CPU Apr 24, 2023
SystemVerilog 2 32-bit RISC-V system on chip for iCE40 FPGAs Jan 20, 2021
SystemVerilog 5 32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs Jan 30, 2022
SystemVerilog 5 A Single Cycle Risc-V 32 bit CPU Apr 04, 2023
Assembly 5 A FPGA friendly 32 bit RISC-V CPU implementation May 26, 2022
Assembly 2 A FPGA friendly 32 bit RISC-V CPU implementation Jul 18, 2022
Assembly 2 A FPGA friendly 32 bit RISC-V CPU implementation Jul 18, 2021
Assembly 1685 A FPGA friendly 32 bit RISC-V CPU implementation Oct 19, 2022
Assembly 2 A FPGA friendly 32 bit RISC-V CPU implementation Nov 05, 2022
Assembly 2 A FPGA friendly 32 bit RISC-V CPU implementation Nov 22, 2022
Verilog 50 A small SoC with a pipeline 32-bit RISC-V CPU. May 10, 2023
VHDL 2 16-bit Posit Adder for FPGAs Dec 08, 2021
CSS 13 The Sherwood Architecture is a custom 64-Bit RISC based CPU architecture. Jan 20, 2022
SystemVerilog 7 [Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core. Feb 24, 2023
SystemVerilog 13 Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip. May 14, 2023
Verilog 3 RISC-V CPU implementation Feb 05, 2022
SystemVerilog 229 RISC-V CPU Core Apr 22, 2023
Verilog 2 32 bit RISC Processor Jun 11, 2021
Verilog 17 32-bit RISC processor May 16, 2022
C++ 2 16-Bit CPU May 03, 2023
VHDL 374 A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz May 11, 2023
Verilog 773 RISC-V CPU Core (RV32IM) Apr 23, 2023
None 2 RISC-V CPU Core (RV32IM) Dec 12, 2021
C++ 12 RISC-V SST CPU Component Apr 19, 2023
Batchfile 3 A pipelined RISC-V CPU Sep 07, 2023
SystemVerilog 787 Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. Aug 12, 2022
None 2 Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. Aug 23, 2021
None 2 Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. May 17, 2021
Objective-C 6 RISC-V CPU plugin for Hopper Disassembler Oct 26, 2019
Assembly 65 RISC-V CPU for OpenFPGAs, in Icestudio Nov 11, 2022
None 2 RISC-V-CPU Study Group for Eklavya Sep 14, 2022
C 36 Yocto project for Xuantie RISC-V CPU Dec 31, 2022
C 8 32-bit RISC-V microcontroller May 11, 2022
C 16 32-bit RISC-V Emulator Mar 02, 2022
C 2 RISC-V 64-bit kernel Oct 12, 2022
VHDL 14 A bit-serial CPU Feb 28, 2022
C++ 253 16-bit homebrew CPU Aug 12, 2022
Python 8 Homebrew 8-bit CPU Jan 11, 2023
Shell 19 GDB Server for interacting with RISC-V models, boards and FPGAs Jan 30, 2023
C++ 3 Assembler for 16-bit EEP0 CPU. May 04, 2022
VHDL 2 8-bit CPU made for FPGA Oct 02, 2022
C 2 Yet another RISC-V CPU core Aug 16, 2020
Verilog 2 SERV - The SErial RISC-V CPU Jan 29, 2022
Scala 41 MR1 formally verified RISC-V CPU Apr 27, 2023
Verilog 2 SERV - The SErial RISC-V CPU Jan 20, 2021
None 2 SERV - The SErial RISC-V CPU Oct 04, 2022
Verilog 958 SERV - The SErial RISC-V CPU Apr 26, 2023
SystemVerilog 5 RISC-V five stage pipline CPU Mar 24, 2023
Verilog 6 A RISC CPU instruction set for academy experiment Mar 23, 2020
Roff 29 Buildroot customized for Xuantie™ RISC-V CPU Apr 11, 2023