EGo1-Vivado-Lock

FPGA设计，借助Vivado和Ego1实验平台设计的密码锁【内附报告】（FPGA design, password lock designed by vivado and ego1 experimental platform [attached report]）

Stars

5

Forks

0

Language

Verilog

Last Updated

Dec 04, 2023

Similar Repos
Repo Language Stars Description Updated At
Jupyter Notebook 20 Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for … May 04, 2023
VHDL 18 Vivado design for basic NeTV2 FPGA with chroma-based overlay Jun 10, 2022
Jupyter Notebook 22 Contains FPGA benchmarks for Vivado HLS and Catapult HLS Dec 09, 2022
Makefile 6 Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more Oct 04, 2023
VHDL 2 Collection of gen3 readout FPGA blocks and submodules for Vivado Sep 16, 2021
VHDL 27 FPGA development platform for high-performance RF and digital design Nov 15, 2022
Go 2 :lock: A simple, secure and personal password manager. Mar 21, 2022
C++ 102 [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS. Apr 26, 2023
Python 93 [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs. Apr 26, 2023
None 2 [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs. May 04, 2023
JavaScript 2 Performance and Error Report Platform Oct 15, 2017
JavaScript 82 :seedling: Experimental open FPGA IDE using Atom and Apio Feb 15, 2023
VHDL 3 FPGA design and test files for ChipWhisperer-Husky. Mar 13, 2023
HTML 6 Blocking and randomization for experimental design Jan 09, 2023
Python 4 基于FPGA的癫痫预测平台设计Design of epilepsy prediction platform based on FPGA Oct 25, 2022
Verilog 3 This project includes 4 bit configuration of Datapath and controller of shift and add sequential … Dec 26, 2023
JavaScript 43 Experimental content sharing and collaboration platform. Jul 09, 2022
JavaScript 49 :lock::mag: Combine jQuery and zxcvbn to create a password strength meter Dec 06, 2021
Jupyter Notebook 50 Experimental design and (multi-objective) bayesian optimization. Apr 23, 2023
Python 11 DSL for experimental design and statistical analysis Apr 28, 2023
Swift 2 Cross platform lock inspired by and compatible with OSAllocatedUnfairLock Jan 12, 2024
HTML 2 samsung s8 lock screen design using html and tailwind css Jan 07, 2022
PHP 632 Design presentation and collaboration platform Aug 15, 2022
C 2 Concurrency Kit provides a plethora of concurrency primitives, safe memory reclamation mechanisms and lock-less and … Sep 17, 2013
Go 2 Cross platform Picturelife uploader - experimental and unsupported Jul 27, 2015
C 7 This repository documents Interfacing HDMI and VGA with Pynq Z2 Board using Vivado block design … Apr 24, 2023
CSS 3 jQuery plugin designed to view and copy password as plain text from password type fields. Nov 08, 2021
TypeScript 3 Experimental design system exploration with React and Stitches. Mar 07, 2023
Verilog 3 SJTU CS145 Computer Architecture Labs. Apr 08, 2022
Verilog 4 This is the design experiment of a third-year computer composition principle course in a university. … Mar 15, 2021
Verilog 4 Skywater 130nm LDO parts and DPLL May 03, 2022
    CREME_DIGITAL
Verilog 4 None Apr 11, 2022
Verilog 4 [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs Mar 27, 2022
Verilog 4 UVM Testbench for Keccak sha3 core downloaded from Opencores https://opencores.org/projects/sha3 Mar 30, 2022
    axi4lite_sha3
Verilog 4 None Jun 02, 2022
Verilog 4 Comprehensive hardware library in Verilog for hardware primitives Oct 30, 2021
Verilog 4 Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor … May 25, 2022
    RealCPU
Verilog 4 None Jun 07, 2022
    cpu
Verilog 4 None Jan 04, 2022
Verilog 4 FIFO implementation with different clock domains for read and write. Jun 16, 2022
Verilog 4 鉴于网上RISC v版单周期CPU完整资料较少，基本无能够直接运行版本，上传代码，仅供大家参考。相关问题可以联系作者[email protected]。 Jul 05, 2022
    caravel-LoesterSoC
Verilog 4 None Apr 14, 2022
Verilog 4 Import of the demon core from SVN http://gadgetforge.gadgetfactory.net/svn/butterflylogic/trunk/Verilog_Core/ Jul 19, 2016
Verilog 4 Single-cycle and pipelined MIPS CPUs written for learning purpose. Written in 12 hours. Jun 21, 2022
Verilog 4 The AY-3-8500 Pong-on-a-chip for the Ulx3s ECP5 board Jul 18, 2022
Verilog 4 Version of Ice40Beeb for Ulx3s ECP5 board Jul 18, 2022
Verilog 4 ColecoVision console for the Ulx3s ECP5 board Jul 18, 2022
Verilog 4 Sega Master System for Ulx3s ECP5 FPGA Jul 18, 2022
Verilog 4 Minimal Commodore Vic 20 core for the Ulx3s ECP5 board Jul 18, 2022
Verilog 4 "High density" digital standard cells for SKY130 provided by SkyWater. Jul 31, 2022