cpus-cadr

MIT CADR original verilog and simulator

Stars

15

Forks

2

Language

Verilog

Last Updated

Mar 13, 2023

Similar Repos
Repo Language Stars Description Updated At
Verilog 4 Verilog-Based-NoC-Simulator Oct 30, 2019
Rich Text Format 2 A simple, easy, and fast Verilog simulator. Oct 19, 2022
Rust 4 Tiny verilog event loop simulator Jun 26, 2022
Perl 2 Dockerfile for OSS CVC verilog simulator Jan 26, 2022
Verilog 41 The Original Nintendo Gameboy in Verilog May 03, 2023
C 9 Y86-64 Tools: assembler, simulator, Verilog designs Feb 03, 2022
F# 2 Verilog Block Simulator (EE3 HLP 2020 coursework) Dec 03, 2020
Verilog 2 Simple simulator of MIPS CPU written in Verilog Sep 07, 2022
Verilog 97 FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs May 31, 2023
Verilog 3 Single Cycle & 5-stage Pipelined MIPS Simulator in Verilog Mar 11, 2023
Python 4 An interactive digital logic simulator with verilog support (Yosys) May 10, 2023
Python 4 Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL. Aug 09, 2022
Python 178 VHDL/Verilog/SystemC code generator, simulator API written in python/c++ Apr 21, 2023
Rust 2 A simple mapreduce implementation heavily influenced by MIT 6.824 and the original paper. Mar 06, 2023
Verilog 3 SJTU CS145 Computer Architecture Labs. Apr 08, 2022
Verilog 4 This is the design experiment of a third-year computer composition principle course in a university. … Mar 15, 2021
Verilog 4 Skywater 130nm LDO parts and DPLL May 03, 2022
    CREME_DIGITAL
Verilog 4 None Apr 11, 2022
Verilog 4 [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs Mar 27, 2022
Verilog 4 UVM Testbench for Keccak sha3 core downloaded from Opencores https://opencores.org/projects/sha3 Mar 30, 2022
    axi4lite_sha3
Verilog 4 None Jun 02, 2022
Verilog 4 Comprehensive hardware library in Verilog for hardware primitives Oct 30, 2021
Verilog 4 Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor … May 25, 2022
    RealCPU
Verilog 4 None Jun 07, 2022
    cpu
Verilog 4 None Jan 04, 2022
Verilog 4 FIFO implementation with different clock domains for read and write. Jun 16, 2022
Verilog 4 鉴于网上RISC v版单周期CPU完整资料较少，基本无能够直接运行版本，上传代码，仅供大家参考。相关问题可以联系作者[email protected]。 Jul 05, 2022
    caravel-LoesterSoC
Verilog 4 None Apr 14, 2022
Verilog 4 Import of the demon core from SVN http://gadgetforge.gadgetfactory.net/svn/butterflylogic/trunk/Verilog_Core/ Jul 19, 2016
Verilog 4 Single-cycle and pipelined MIPS CPUs written for learning purpose. Written in 12 hours. Jun 21, 2022
Verilog 4 The AY-3-8500 Pong-on-a-chip for the Ulx3s ECP5 board Jul 18, 2022
Verilog 4 Version of Ice40Beeb for Ulx3s ECP5 board Jul 18, 2022
Verilog 4 ColecoVision console for the Ulx3s ECP5 board Jul 18, 2022
Verilog 4 Sega Master System for Ulx3s ECP5 FPGA Jul 18, 2022
Verilog 4 Minimal Commodore Vic 20 core for the Ulx3s ECP5 board Jul 18, 2022
Verilog 4 "High density" digital standard cells for SKY130 provided by SkyWater. Jul 31, 2022
Verilog 4 "Low speed" digital standard cells for SKY130 provided by SkyWater. Jul 31, 2022
    openrcx-calibration
Verilog 4 None Aug 06, 2022
    ice40
Verilog 4 None Jan 20, 2022
    fpga-lvds-ddr
Verilog 4 None Mar 17, 2022
    mph-tristate-test
Verilog 4 None Mar 17, 2022
    multi-project-harness
Verilog 4 None Mar 12, 2021
Verilog 4 Demo project for Zero to ASIC course & presentations Jun 01, 2022
    caravel_aes
Verilog 4 None Oct 10, 2021
Verilog 4 Verilog CPU design for MIPS instructions Jan 19, 2021
Verilog 4 Class project implementing Reorder Buffer in Tomasula Algorithm Aug 03, 2022
Verilog 4 ComProc project home Apr 29, 2022
Verilog 4 uchan's Electronics laboratory. Experimental projects. Apr 17, 2022
Verilog 4 Verilog RTL Design Jul 15, 2022
Verilog 4 THUEE Course: Experiments of Digital Logic and Processor May 08, 2021