|
JavaScript |
8 |
global-replace-console-log |
Nov 19, 2021 |
|
C++ |
8 |
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing” |
Oct 31, 2022 |
|
C++ |
16 |
Annealing-based PCB placement tool |
Jun 25, 2022 |
|
C++ |
6 |
VLSI placement and routing tool |
Apr 23, 2023 |
|
C++ |
14 |
Macro placement tool for OpenROAD flow |
Jun 29, 2022 |
|
JavaScript |
2 |
i18n-extract-replace-tool |
Nov 08, 2021 |
|
JavaScript |
2 |
Browserify transform to replace global variables with custom content |
Dec 13, 2016 |
|
Rust |
340 |
A code search / replace tool |
Aug 09, 2022 |
|
Go |
4 |
Recursive search and replace tool |
Sep 20, 2022 |
|
Rust |
2 |
Intuitive find and replace tool |
Mar 09, 2023 |
|
Verilog |
3 |
SJTU CS145 Computer Architecture Labs. |
Apr 08, 2022 |
|
Verilog |
4 |
This is the design experiment of a third-year computer composition principle course in a university. … |
Mar 15, 2021 |
|
Verilog |
4 |
Skywater 130nm LDO parts and DPLL |
May 03, 2022 |
|
Verilog |
4 |
None |
Apr 11, 2022 |
|
Verilog |
4 |
[DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs |
Mar 27, 2022 |
|
Verilog |
4 |
UVM Testbench for Keccak sha3 core downloaded from Opencores https://opencores.org/projects/sha3 |
Mar 30, 2022 |
|
Verilog |
4 |
None |
Jun 02, 2022 |
|
Verilog |
4 |
Comprehensive hardware library in Verilog for hardware primitives |
Oct 30, 2021 |
|
Verilog |
4 |
Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor … |
May 25, 2022 |
|
Verilog |
4 |
None |
Jun 07, 2022 |
|
Verilog |
4 |
None |
Jan 04, 2022 |
|
Verilog |
4 |
FIFO implementation with different clock domains for read and write. |
Jun 16, 2022 |
|
Verilog |
4 |
鉴于网上RISC v版单周期CPU完整资料较少,基本无能够直接运行版本,上传代码,仅供大家参考。相关问题可以联系作者[email protected]。 |
Jul 05, 2022 |
|
Verilog |
4 |
None |
Apr 14, 2022 |
|
Verilog |
4 |
Import of the demon core from SVN http://gadgetforge.gadgetfactory.net/svn/butterflylogic/trunk/Verilog_Core/ |
Jul 19, 2016 |
|
Verilog |
4 |
Single-cycle and pipelined MIPS CPUs written for learning purpose. Written in 12 hours. |
Jun 21, 2022 |
|
Verilog |
4 |
The AY-3-8500 Pong-on-a-chip for the Ulx3s ECP5 board |
Jul 18, 2022 |
|
Verilog |
4 |
Version of Ice40Beeb for Ulx3s ECP5 board |
Jul 18, 2022 |
|
Verilog |
4 |
ColecoVision console for the Ulx3s ECP5 board |
Jul 18, 2022 |
|
Verilog |
4 |
Sega Master System for Ulx3s ECP5 FPGA |
Jul 18, 2022 |
|
Verilog |
4 |
Minimal Commodore Vic 20 core for the Ulx3s ECP5 board |
Jul 18, 2022 |
|
Verilog |
4 |
"High density" digital standard cells for SKY130 provided by SkyWater. |
Jul 31, 2022 |
|
Verilog |
4 |
"Low speed" digital standard cells for SKY130 provided by SkyWater. |
Jul 31, 2022 |
|
Verilog |
4 |
None |
Aug 06, 2022 |
|
Verilog |
4 |
Verilog-Based-NoC-Simulator |
Oct 30, 2019 |
|
Verilog |
4 |
None |
Jan 20, 2022 |
|
Verilog |
4 |
None |
Mar 17, 2022 |
|
Verilog |
4 |
None |
Mar 17, 2022 |
|
Verilog |
4 |
None |
Mar 12, 2021 |
|
Verilog |
4 |
Demo project for Zero to ASIC course & presentations |
Jun 01, 2022 |
|
Verilog |
4 |
None |
Oct 10, 2021 |
|
Verilog |
4 |
Verilog CPU design for MIPS instructions |
Jan 19, 2021 |
|
Verilog |
4 |
Class project implementing Reorder Buffer in Tomasula Algorithm |
Aug 03, 2022 |
|
Verilog |
4 |
ComProc project home |
Apr 29, 2022 |
|
Verilog |
4 |
uchan's Electronics laboratory. Experimental projects. |
Apr 17, 2022 |
|
Verilog |
4 |
Verilog RTL Design |
Jul 15, 2022 |
|
Verilog |
4 |
THUEE Course: Experiments of Digital Logic and Processor |
May 08, 2021 |
|
Verilog |
4 |
None |
Aug 04, 2021 |
|
Verilog |
4 |
None |
Mar 22, 2022 |
|
Verilog |
4 |
None |
Feb 14, 2021 |