|
Roff |
29 |
Buildroot customized for Xuantie™ RISC-V CPU |
Apr 11, 2023 |
|
None |
9 |
GCC for Xuantie RISC-V CPU, the GNU Compiler Collection. |
May 03, 2023 |
|
C |
440 |
Patches & Script for AOSP to run on Xuantie RISC-V CPU |
Apr 11, 2023 |
|
C |
49 |
GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils …… |
Apr 20, 2023 |
|
None |
8 |
Binutils/GDB for Xuantie RISC-V CPU, a collection of binary tools. |
Dec 31, 2022 |
|
C |
15 |
Qemu for Xuantie RISC-V CPU, a generic machine emulator and virtualizer. |
Mar 23, 2023 |
|
C |
2 |
Qemu for Xuantie RISC-V CPU, a generic machine emulator and virtualizer. |
Feb 21, 2024 |
|
C |
6 |
Newlib for Xuantie RISC-V CPU, a lightweight C library for embedded systems. |
Dec 31, 2022 |
|
C |
6 |
GNU project's implementation of the standard C library(with Xuantie RISC-V CPU support). |
Dec 31, 2022 |
|
None |
8 |
LLVM for Xuantie RISC-V CPU, a collection of modular and reusable compiler and toolchain technologies. |
May 31, 2022 |
|
BitBake |
269 |
OpenEmbedded/Yocto layer for RISC-V Architecture |
Apr 21, 2023 |
|
None |
61 |
Port of the Yocto Project to the RISC-V ISA |
Jun 28, 2021 |
|
Rust |
30 |
Low level access to T-Head Xuantie RISC-V processors |
Aug 24, 2022 |
|
Verilog |
3 |
RISC-V CPU implementation |
Feb 05, 2022 |
|
SystemVerilog |
229 |
RISC-V CPU Core |
Apr 22, 2023 |
|
C |
43 |
An optimized neural network operator library for chips base on Xuantie CPU. |
Apr 21, 2023 |
|
Python |
16 |
TVM for chips base on Xuantie CPU, an open deep learning compiler stack. |
Apr 28, 2023 |
|
Verilog |
773 |
RISC-V CPU Core (RV32IM) |
Apr 23, 2023 |
|
None |
2 |
RISC-V CPU Core (RV32IM) |
Dec 12, 2021 |
|
C++ |
12 |
RISC-V SST CPU Component |
Apr 19, 2023 |
|
Batchfile |
3 |
A pipelined RISC-V CPU |
Sep 07, 2023 |
|
Objective-C |
6 |
RISC-V CPU plugin for Hopper Disassembler |
Oct 26, 2019 |
|
Assembly |
65 |
RISC-V CPU for OpenFPGAs, in Icestudio |
Nov 11, 2022 |
|
None |
2 |
RISC-V-CPU Study Group for Eklavya |
Sep 14, 2022 |
|
C |
32 |
"Yun", aka cloud, On Chip (YoC) is based on AliOS Things for Xuantie RISC-V CPU … |
Feb 03, 2023 |
|
C |
2 |
Yet another RISC-V CPU core |
Aug 16, 2020 |
|
Verilog |
2 |
SERV - The SErial RISC-V CPU |
Jan 29, 2022 |
|
Verilog |
567 |
32-bit Superscalar RISC-V CPU |
Apr 24, 2023 |
|
Scala |
41 |
MR1 formally verified RISC-V CPU |
Apr 27, 2023 |
|
Verilog |
2 |
SERV - The SErial RISC-V CPU |
Jan 20, 2021 |
|
None |
2 |
SERV - The SErial RISC-V CPU |
Oct 04, 2022 |
|
Verilog |
958 |
SERV - The SErial RISC-V CPU |
Apr 26, 2023 |
|
SystemVerilog |
5 |
RISC-V five stage pipline CPU |
Mar 24, 2023 |
|
Verilog |
6 |
A RISC CPU instruction set for academy experiment |
Mar 23, 2020 |
|
VHDL |
12 |
My 32-bit RISC CPU for smallish FPGAs |
Feb 01, 2023 |
|
SystemVerilog |
4 |
まともなRISC-V CPU |
Jul 18, 2022 |
|
Verilog |
7 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Mar 17, 2022 |
|
Verilog |
2088 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Aug 14, 2022 |
|
Verilog |
2 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Dec 02, 2021 |
|
Python |
3 |
UCB-CS61C project3 : RISC-V CPU design |
Mar 19, 2023 |
|
SystemVerilog |
2 |
RISC-V RV32I CPU core in SystemVerilog |
Mar 14, 2023 |
|
Verilog |
2 |
5段パイプラインのRISC-V CPU |
Aug 07, 2020 |
|
None |
2 |
RISC V Pipelined discrete CPU using logism |
Mar 15, 2022 |
|
Verilog |
3 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Dec 02, 2021 |
|
Verilog |
18 |
RISC-VのCPU作った |
Nov 20, 2021 |
|
Verilog |
2 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Dec 02, 2021 |
|
None |
2 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Mar 28, 2022 |
|
Verilog |
2 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Mar 16, 2022 |
|
VHDL |
3 |
Simple CPU on Risc-V @Zhejiang University |
Mar 20, 2023 |
|
Verilog |
2 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Mar 17, 2022 |