|
Objective-C |
22 |
Experimental MIPS CPU plugin for the Hopper Disassembler |
Apr 01, 2021 |
|
Objective-C |
9 |
PSX Loader plugin for Hopper Disassembler |
Nov 21, 2021 |
|
Python |
32 |
Scripts for Hopper Disassembler |
May 13, 2023 |
|
Objective-C |
3 |
CGC (Cyber Grand Challenge) binary loader plugin for Hopper Disassembler |
Nov 07, 2020 |
|
None |
7 |
Xcode templates for Hopper Disassembler SDK |
Dec 16, 2021 |
|
Python |
6 |
Hopper Disassembler scripts for OS X |
Jun 02, 2022 |
|
Objective-C |
10 |
Unofficial Hopper Disassembler SDK mirror |
Nov 24, 2021 |
|
Objective-C |
6 |
ARM Image Format loader for Hopper disassembler |
Jul 18, 2021 |
|
Python |
2 |
Python Scripts for use with Hopper Disassembler |
Jan 11, 2023 |
|
C |
10 |
A plugin for Hopper Disassembler which adds support for Hitachi SH4. (Dreamcast) |
May 17, 2023 |
|
Objective-C |
20 |
A Gamecube/Wii .DOL loader and Gecko PPC plugin for Hopper Disassembler |
May 06, 2022 |
|
Go |
3 |
RISC-V Disassembler |
Mar 02, 2023 |
|
Python |
15 |
Hopper Disassembler v5 scripts, focus on iOS/macOS |
Apr 02, 2023 |
|
Rust |
2 |
RISC-V disassembler crate for Rust |
Dec 17, 2020 |
|
C |
2 |
Disassembler for Rendition Verite V1000/V2000 RISC |
Apr 27, 2023 |
|
None |
52 |
Doyensec theme for the Hopper Disassembler - chill and functional for long RE nights |
Dec 04, 2022 |
|
Verilog |
3 |
RISC-V CPU implementation |
Feb 05, 2022 |
|
SystemVerilog |
229 |
RISC-V CPU Core |
Apr 22, 2023 |
|
Verilog |
773 |
RISC-V CPU Core (RV32IM) |
Apr 23, 2023 |
|
None |
2 |
RISC-V CPU Core (RV32IM) |
Dec 12, 2021 |
|
C++ |
12 |
RISC-V SST CPU Component |
Apr 19, 2023 |
|
Batchfile |
3 |
A pipelined RISC-V CPU |
Sep 07, 2023 |
|
Python |
5 |
Tiny Python LC3 CPU emulator and disassembler |
Apr 17, 2022 |
|
C |
73 |
RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC |
Apr 30, 2023 |
|
Assembly |
65 |
RISC-V CPU for OpenFPGAs, in Icestudio |
Nov 11, 2022 |
|
None |
2 |
RISC-V-CPU Study Group for Eklavya |
Sep 14, 2022 |
|
C |
36 |
Yocto project for Xuantie RISC-V CPU |
Dec 31, 2022 |
|
HTML |
22 |
Xtensa CPU architecture (ESP8266) binaries for ScratchABit interactive disassembler |
May 22, 2022 |
|
Objective-C |
7 |
A Hopper plugin for demangle Swift symbols |
Nov 18, 2016 |
|
Objective-C |
509 |
A Hopper plugin for demangle Swift symbols |
Aug 23, 2022 |
|
C |
2 |
Yet another RISC-V CPU core |
Aug 16, 2020 |
|
Verilog |
2 |
SERV - The SErial RISC-V CPU |
Jan 29, 2022 |
|
Verilog |
567 |
32-bit Superscalar RISC-V CPU |
Apr 24, 2023 |
|
Scala |
41 |
MR1 formally verified RISC-V CPU |
Apr 27, 2023 |
|
Verilog |
2 |
SERV - The SErial RISC-V CPU |
Jan 20, 2021 |
|
None |
2 |
SERV - The SErial RISC-V CPU |
Oct 04, 2022 |
|
Verilog |
958 |
SERV - The SErial RISC-V CPU |
Apr 26, 2023 |
|
SystemVerilog |
5 |
RISC-V five stage pipline CPU |
Mar 24, 2023 |
|
Verilog |
6 |
A RISC CPU instruction set for academy experiment |
Mar 23, 2020 |
|
VHDL |
12 |
My 32-bit RISC CPU for smallish FPGAs |
Feb 01, 2023 |
|
Roff |
29 |
Buildroot customized for Xuantie™ RISC-V CPU |
Apr 11, 2023 |
|
C |
10 |
Mini RISC-V toolchain for Linux consisting of compiler, simulator and disassembler. |
Dec 02, 2022 |
|
Go |
43 |
6502 CPU emulator, assembler and disassembler written in Go |
May 09, 2023 |
|
SystemVerilog |
4 |
まともなRISC-V CPU |
Jul 18, 2022 |
|
Verilog |
7 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Mar 17, 2022 |
|
Verilog |
2088 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Aug 14, 2022 |
|
Verilog |
2 |
PicoRV32 - A Size-Optimized RISC-V CPU |
Dec 02, 2021 |
|
Python |
3 |
UCB-CS61C project3 : RISC-V CPU design |
Mar 19, 2023 |
|
SystemVerilog |
2 |
RISC-V RV32I CPU core in SystemVerilog |
Mar 14, 2023 |
|
Verilog |
2 |
5段パイプラインのRISC-V CPU |
Aug 07, 2020 |