serv

SERV - The SErial RISC-V CPU

Stars

2

Forks

1

Language

Verilog

Last Updated

Jan 29, 2022

Similar Repos
Repo Language Stars Description Updated At
Verilog 2 SERV - The SErial RISC-V CPU Jan 20, 2021
None 2 SERV - The SErial RISC-V CPU Oct 04, 2022
Verilog 958 SERV - The SErial RISC-V CPU Apr 26, 2023
Verilog 27 SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from … Apr 29, 2023
SystemVerilog 16 SERV RISC-V sample for Tang Nano FPGA board Jan 11, 2023
Verilog 3 RISC-V CPU implementation Feb 05, 2022
SystemVerilog 229 RISC-V CPU Core Apr 22, 2023
VHDL 14 A bit-serial CPU Feb 28, 2022
Verilog 773 RISC-V CPU Core (RV32IM) Apr 23, 2023
None 2 RISC-V CPU Core (RV32IM) Dec 12, 2021
C++ 12 RISC-V SST CPU Component Apr 19, 2023
Batchfile 3 A pipelined RISC-V CPU Sep 07, 2023
Scala 2 reimplementation of the serv core in Chisel (https://github.com/olofk/serv) Mar 19, 2022
Verilog 4 Python module containing verilog files for serv cpu (for use with LiteX). Jan 02, 2023
None 35 Allnet serv. Apr 30, 2023
C 2 Yet another RISC-V CPU core Aug 16, 2020
Verilog 567 32-bit Superscalar RISC-V CPU Apr 24, 2023
Scala 41 MR1 formally verified RISC-V CPU Apr 27, 2023
SystemVerilog 5 RISC-V five stage pipline CPU Mar 24, 2023
SystemVerilog 4 まともなRISC-V CPU Jul 18, 2022
Objective-C 6 RISC-V CPU plugin for Hopper Disassembler Oct 26, 2019
Verilog 7 PicoRV32 - A Size-Optimized RISC-V CPU Mar 17, 2022
Verilog 2088 PicoRV32 - A Size-Optimized RISC-V CPU Aug 14, 2022
Verilog 2 PicoRV32 - A Size-Optimized RISC-V CPU Dec 02, 2021
Assembly 65 RISC-V CPU for OpenFPGAs, in Icestudio Nov 11, 2022
Python 3 UCB-CS61C project3 : RISC-V CPU design Mar 19, 2023
SystemVerilog 2 RISC-V RV32I CPU core in SystemVerilog Mar 14, 2023
Verilog 2 5段パイプラインのRISC-V CPU Aug 07, 2020
None 2 RISC V Pipelined discrete CPU using logism Mar 15, 2022
Verilog 3 PicoRV32 - A Size-Optimized RISC-V CPU Dec 02, 2021
Verilog 18 RISC-VのCPU作った Nov 20, 2021
Verilog 2 PicoRV32 - A Size-Optimized RISC-V CPU Dec 02, 2021
None 2 PicoRV32 - A Size-Optimized RISC-V CPU Mar 28, 2022
Verilog 2 PicoRV32 - A Size-Optimized RISC-V CPU Mar 16, 2022
None 2 RISC-V-CPU Study Group for Eklavya Sep 14, 2022
VHDL 3 Simple CPU on Risc-V @Zhejiang University Mar 20, 2023
C 36 Yocto project for Xuantie RISC-V CPU Dec 31, 2022
Verilog 2 PicoRV32 - A Size-Optimized RISC-V CPU Mar 17, 2022
Verilog 2 PicoRV32 - A Size-Optimized RISC-V CPU Jun 15, 2023
Verilog 2 Pipelined CPU microarchitecture RISC-V ISA RV32I. Dec 09, 2023
None 9 GCC for Xuantie RISC-V CPU, the GNU Compiler Collection. May 03, 2023
Verilog 6 A RISC CPU instruction set for academy experiment Mar 23, 2020
SystemVerilog 46 Ariane is a 6-stage RISC-V CPU Jun 25, 2022
Scala 3 A basic RISC-V CPU written in Chisel Apr 12, 2021
None 18 RISC-V RV32IM cpu circuit in Logisim Evolution. Feb 08, 2023
Verilog 2 A small, light weight, RISC CPU soft core Jan 27, 2023
SystemVerilog 5 A Single Cycle Risc-V 32 bit CPU Apr 04, 2023
VHDL 12 My 32-bit RISC CPU for smallish FPGAs Feb 01, 2023
Verilog 1028 A small, light weight, RISC CPU soft core May 05, 2023
Roff 29 Buildroot customized for Xuantie™ RISC-V CPU Apr 11, 2023