|
Verilog |
122 |
A 32-bit Microcontroller featuring a RISC-V core |
Jul 17, 2022 |
|
SystemVerilog |
7 |
[Deprecated] Azadi is an SoC with 32 bit RISC-V CPU core. |
Feb 24, 2023 |
|
SystemVerilog |
4 |
cayde is 32-bit RISC-V core written in SystemVerilog |
Apr 02, 2023 |
|
C |
42 |
NucleusRV - A 32-bit 5 staged pipelined risc-v core. |
May 25, 2023 |
|
Verilog |
2 |
32 bit RISC Processor |
Jun 11, 2021 |
|
Verilog |
17 |
32-bit RISC processor |
May 16, 2022 |
|
Verilog |
2 |
RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core. |
Dec 15, 2023 |
|
C |
8 |
32-bit RISC-V microcontroller |
May 11, 2022 |
|
C |
16 |
32-bit RISC-V Emulator |
Mar 02, 2022 |
|
C |
2 |
RISC-V 64-bit kernel |
Oct 12, 2022 |
|
Assembly |
18 |
A minimalist 8-bit microcomputer with stack-based microprocessor |
May 03, 2023 |
|
Verilog |
5 |
Simple Pipelined 32 bit RISC Processor |
Jul 16, 2022 |
|
SystemVerilog |
9 |
64-bit multicore RISC-V processor |
Aug 05, 2022 |
|
Verilog |
567 |
32-bit Superscalar RISC-V CPU |
Apr 24, 2023 |
|
Go |
7 |
32/64-bit RISC-V emulator |
Jan 06, 2023 |
|
Python |
2 |
RISC-V Bit Manipulation ISA Extension |
Mar 04, 2023 |
|
VHDL |
374 |
A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz |
May 11, 2023 |
|
SystemVerilog |
229 |
RISC-V CPU Core |
Apr 22, 2023 |
|
SystemVerilog |
787 |
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. |
Aug 12, 2022 |
|
None |
2 |
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. |
Aug 23, 2021 |
|
None |
2 |
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. |
May 17, 2021 |
|
HTML |
11 |
RISC-V Ibex core with Wishbone B4 interface |
Dec 27, 2022 |
|
Python |
247 |
A 32-bit RISC-V soft processor |
Jun 12, 2022 |
|
Makefile |
16 |
RISC-V 32-bit Linux From Scratch |
Mar 27, 2023 |
|
Python |
2 |
A 32-bit RISC-V soft processor |
Feb 28, 2023 |
|
Verilog |
4 |
32 bit Risc-5 mimari işlemci tasarımı |
May 31, 2023 |
|
Rust |
13 |
Rust RISC-V Simulator |
Apr 05, 2023 |
|
Batchfile |
4 |
32-Bit RISC inspired Processor with Von Neumann Architecture using Logisim |
May 21, 2022 |
|
C |
31 |
A 32-bit RISC-V Processor Designed with High-Level Synthesis |
Apr 25, 2023 |
|
Verilog |
50 |
A small SoC with a pipeline 32-bit RISC-V CPU. |
May 10, 2023 |
|
Rust |
2 |
Risc-V assembly interpreter built with pure Rust |
Aug 24, 2022 |
|
None |
3 |
RISC-V Core Test Framework |
Feb 08, 2023 |
|
Verilog |
773 |
RISC-V CPU Core (RV32IM) |
Apr 23, 2023 |
|
None |
2 |
RISC-V CPU Core (RV32IM) |
Dec 12, 2021 |
|
Haskell |
2 |
Functionally described RISC-V core |
Jan 04, 2020 |
|
C++ |
128 |
🤩 Emoji shellcoding tools for RISC-V (32-bit and 64-bit) |
May 29, 2023 |
|
C |
68 |
A minimalist RISC-V emulator capable of running xv6 |
Aug 28, 2022 |
|
SystemVerilog |
8 |
Open-Source Posit RISC-V Core with Quire Capability |
May 19, 2022 |
|
Verilog |
14 |
Dual-core RISC-V SoC with JTAG, atomics, SDRAM |
Aug 02, 2022 |
|
Verilog |
3 |
RTL to GDSII for RISC V Core with SRAM |
Jun 19, 2023 |
|
SystemVerilog |
5 |
A Single Cycle Risc-V 32 bit CPU |
Apr 04, 2023 |
|
VHDL |
12 |
My 32-bit RISC CPU for smallish FPGAs |
Feb 01, 2023 |
|
Verilog |
3 |
Verilog implementation of the 32-bit RISC processor. |
May 23, 2022 |
|
JavaScript |
86 |
The minimalist jsreport rendering core |
Mar 21, 2023 |
|
JavaScript |
4 |
A minimalist template for building Electron apps with React. |
Jan 31, 2021 |
|
Rust |
9 |
Rust examples for RISC Zero |
Jun 17, 2022 |
|
Rust |
67 |
Rust RISC-V Virtual Machine |
Apr 09, 2023 |
|
Rust |
27 |
Bit-vectors and bit-slices for Rust |
Mar 28, 2023 |
|
Rust |
92 |
Minimalist rsync implementation in Rust |
Aug 17, 2022 |
|
C |
2 |
Yet another RISC-V CPU core |
Aug 16, 2020 |